Multi-stage secure clusterhead selection using discrete rule-set against unknown attacks in wireless sensor network

Security is the rising concern of the wireless network as there are various forms of reonfigurable network that is arised from it. Wireless sensor network (WSN) is one such example that is found to be an integral part of cyber-physical system in upcoming times. After reviewing the existing system, it can be seen that there are less dominant and robust solutions towards mitigating the threats of upcoming applications of WSN. Therefore, this paper introduces a simple and cost-effective modelling of a security system that offers security by ensuring secure selection of clusterhead during the data aggregation process in WSN. The proposed system also makes construct a rule-set in order to learn the nature of the communication iin order to have a discrete knowledge about the intensity of adversaries. With an aid of simulation-based approach over MEMSIC nodes, the proposed system was proven to offer reduced energy consumption with good data delivery performance in contrast to existing approach

Hardware realization of discrete wavelet transform cauchy Reed Solomon minimal instruction set computer architecture for wireless visual sensor networks

Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs

Hardware realization of discrete wavelet transform cauchy Reed Solomon minimal instruction set computer architecture for wireless visual sensor networks

Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs

High Speed Implementation Of Authenticated Encryption For The Msp430x Microcontroller

Authenticated encryption is a symmetric cryptography scheme that provides both confidentiality and authentication. In this work we describe an optimized implementation of authenticated encryption for the MSP430X family of microcontrollers. The CCM, GCM, SGCM, OCB3, Hummingbird-2 and MASHA authenticated encryption schemes were implemented at the 128-bit level of security and their performance was compared. The AES accelerator included in some models of the MSP430X family is also studied and we explore its characteristics to improve the performance of the implemented modes, achieving up to 10 times of speedup. The CCM and OCB3 schemes were the fastest when using the AES accelerator while MASHA and Hummingbird-2 were the fastest when using only software. © 2012 Springer-Verlag.7533 LNCS288304 Intel and McAfee Chile,NIC Chile,Certivox,Center for Mathematical Modeling (CMM) of the University of Chile,INRIA ChileBellare, M., Rogaway, P., Wagner, D., The EAX Mode of Operation (2004) LNCS, 3017, pp. 389-407. , Roy, B., Meier, W. (eds.) FSE 2004. Springer, HeidelbergChai, Q., Gong, G., A cryptanalysis of HummingBird-2: The differential sequence analysis (2012) Cryptology EPrint Archive, , http://eprint.iacr.org/, Report 2012/233Chatterjee, S., Menezes, A., Sarkar, P., Another Look at Tightness LNCS, 7118 (2012), pp. 293-319. , Miri, A., Vaudenay, S. (eds.) SAC 2011. Springer, HeidelbergDidla, S., Ault, A., Bagchi, S., Optimizing AES for embedded devices and wireless sensor networks (2008) Proceedings of the 4th International ICST Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities, pp. 4:1-4:10Engels, D., Saarinen, M.-J.O., Schweitzer, P., Smith, E.M., The Hummingbird-2 Lightweight Authenticated Encryption Algorithm LNCS, 7055 (2012), pp. 19-31. , Juels, A., Paar, C. (eds.) RFIDSec 2011. Springer, HeidelbergGladman, B., (2008) AES and Combined Encryption/authentication Modes, , http://gladman.plushost.co.uk/oldsite/AES/Gouvêa, C.P.L., López, J., Efficient software implementation of public-key cryptography on sensor networks using the MSP430X microcontroller (2012) Journal of Cryptographic Engineering, 2 (1), pp. 19-29(2012) Crypto Software for Microcontrollers - Texas Instruments MSP430 Microcontrollers, , http://jce.iaik.tugraz.at/sic/Products/ Crypto_Software_for_Microcontrollers/Texas_Instruments_MSP430_MicrocontrollersKiyomoto, S., Henricksen, M., Yap, W.-S., Nakano, Y., Fukushima, K., MASHA - Low Cost Authentication with a New Stream Cipher (2011) LNCS, 7001, pp. 63-78. , Lai, X., Zhou, J., Li, H. (eds.) ISC 2011. Springer, HeidelbergKrovetz, T., Rogaway, P., The Software Performance of Authenticated-Encryption Modes (2011) LNCS, 6733, pp. 306-327. , Joux, A. (ed.) FSE 2011. Springer, HeidelbergLim, S.Y., Pu, C.C., Lim, H.T., Lee, H.J., Dragon-MAC: Securing wireless sensor networks with authenticated encryption (2007) Cryptology EPrint Archive, , http://eprint.iacr.org/, Report 2007/204López, J., Dahab, R., High-Speed Software Multiplication in F 2m (2000) LNCS, 1977, pp. 203-212. , Roy, B., Okamoto, E. (eds.) INDOCRYPT 2000. Springer, HeidelbergMcGrew, D.A., Viega, J., The Security and Performance of the Galois/Counter Mode (GCM) of Operation (2004) LNCS, 3348, pp. 343-355. , Canteaut, A., Viswanathan, K. (eds.) INDOCRYPT 2004. Springer, HeidelbergSaarinen, M.J.O., SGCM: The Sophie Germain counter mode (2011) Cryptology EPrint Archive, , http://eprint.iacr.org/, Report 2011/326Simplicio Jr., M.A., Barbuda, P.F.F.S., Barreto, P.S.L.M., Carvalho, T.C.M.B., Margi, C.B., The MARVIN message authentication code and the LETTERSOUP authenticated encryption scheme (2009) Security and Communication Networks, 2 (2), pp. 165-180Simplicio Jr., M.A., De Oliveira, B.T., Barreto, P.S.L.M., Margi, C.B., Carvalho, T.C.M.B., Naslund, M., Comparison of authenticated-encryption schemes in wireless sensor networks (2011) 2011 IEEE 36th Conference on Local Computer Networks (LCN), pp. 450-457Tahir, R., Javed, M., Cheema, A., Rabbit-MAC: Lightweight authenticated encryption in wireless sensor networks (2008) International Conference on Information and Automation, ICIA 2008, pp. 573-577Whiting, D., Housley, R., Ferguson, N., (2002) Counter with CBC-MAC (CCM), , http://csrc.nist.gov/groups/ST/toolkit/BCM/index.htmlZhang, K., Ding, L., Guan, J., Cryptanalysis of Hummingbird-2 (2012) Cryptology EPrint Archive, , http://eprint.iacr.org/, Report 2012/20