The effect of coefficient quantization optimization on filtering performance and gate count

Abstract. Digital filters are an essential component of Digital Signal Processing (DSP) applications and play a crucial role in removing unwanted signal components from a desired signal. However, digital filters are known to be resource-intensive and consume a large amount of power, making it important to optimize their design in order to minimize hardware requirements such as multipliers, adders, and registers. This trade-off between filter performance and hardware consumption can be influenced by the quantization of filter coefficients. Therefore, this thesis investigates the quantization of Finite Impulse Response (FIR) filter coefficients and analyzes its impact on filter performance and hardware resource consumption. A method called dynamic quantization is introduced and an algorithm for step-by-step dynamic quantization is provided to improve upon the results obtained with the classical fixed point quantization method. To demonstrate the effectiveness of this approach, the dynamic quantization of filter coefficients for a Low-pass Equiripple FIR filter is examined and a comparative study of the magnitude response and hardware consumption of the generated filter using both the classical and dynamic quantization methods is presented. By understanding the trade-offs and benefits of each quantization method, engineers can make informed decisions about the most appropriate approach for their specific application

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

Using discrete wavelet transform (DWT) in high-speed signal-processing applications imposes a high degree of care to hardware resource availability, latency, and power consumption. In this chapter, the design aspects and performance of multiplierless DWT is analyzed. We presented the two key multiplierless approaches, namely the distributed arithmetic algorithm (DAA) and the residue number system (RNS). We aim to estimate the performance requirements and hardware resources for each approach, allowing for the selection of proper algorithm and implementation of multi-level DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6’s embedded block RAMs (BRAMs)

M-ary phase-shift keying using finite impulse response filter based on window function method

Digital filters are vastly utilized in the area of communication. A perfect digital filter efficiency is significant and hence to design a digital finite impulse response filter (FIR) favorable all the wanted situations is necessary. In this paper, a new proposed FIR digital filter designed, the fineness of the submitted filter is tested in terms of BER and then matched with another window, namely Hamming, Hanning, and Blackman. The design procedure done in the MATLAB software. It is concluded that the Blackman window is the best window to design the FIR digital filter, because it is bit error rate is better than another window

A low-power asynchronous VLSI FIR filter

An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs

Effective denoising and adaptive equalization of indoor optical wireless channel with artificial light using the discrete wavelet transform and artificial neural network

Indoor diffuse optical wireless (OW) communication systems performance is limited due to a number of effects; interference from natural and artificial light sources and multipath induced intersymbol interference (ISI). Artificial light interference (ALI) is a periodic signal with a spectrum profile extending up to the MHz range. It is the dominant source of performance degradation at low data rates, which can be removed using a high-pass filter (HPF). On the other hand, ISI is more severe at high data rates and an equalizing filter is incorporated at the receiver to compensate for the ISI. This paper provides the simulation results for a discrete wavelet transform (DWT)—artificial neural network (ANN)-based receiver architecture for on-and-off keying (OOK) non-return-to-zero (NRZ) scheme for a diffuse indoor OW link in the presence of ALI and ISI. ANN is adopted for classification acting as an efficient equalizer compared to the traditional equalizers. The ALI is effectively reduced by proper selection of the DWT coefficients resulting in improved receiver performance compared to the digital HPF. The simulated bit error rate (BER) performance of proposed DWT-ANN receiver structure for a diffuse indoor OW link operating at a data range of 10-200 Mbps is presented and discussed. The results are compared with performance of a diffuse link with an HPF-equalizer, ALI with/without filtering, and a line-of-sight (LOS) without filtering. We show that the DWT-ANN display a lower power requirement when compared to the receiver with an HPF-equalizer over a full range of delay spread in presence of ALI. However, as expected compared to the ideal LOS link the power penalty is higher reaching to 6 dB at 200 Mbps data rate