Realization of analog signal processing modules using carbon nanotube field effect transistors

This thesis presents the realization and performance analysis of several carbon nanotube field effect transistor (CNTFET) based analog signal processing (ASP) modules. CNTFET is predicted as a possible successor to conventional silicon complementary metal oxide semiconductor (CMOS), which has reached its scaling limits. The CMOS based ASP modules face significant challenges at deep nanoscale, resulting in severe performance degradations due to short channel effects. The main goal of this work is to realize CNTFET active building blocks (ABBs), and then to utilize these ABBs for realization of low-voltage, low-power, and high-frequency ASP modules. The proposed ABBs have low power dissipation, reduced parasitic components, and minimum number of CNTFETs. The proposed modules are active inductor (AI), first-order phase shifter, and second-order phase shifter. This research proposes a new CNTFET based grounded AI (GAI) circuit with high self-resonance frequency (SRF), wide tunable inductance range, and high quality factor. Simulation results demonstrate that the GAI offers tunable inductance from 4.4 nH to 287.4 nH with a maximum SRF of 101 GHz. It consumes very low power dissipation of 0.337 mW. In comparison to high performance available GAI circuits, the proposed GAI shows 34% reduction in power dissipation and nine times higher SRF. A highfrequency low-noise amplifier (LNA) circuit is also designed by utilizing the proposed GAI to showcase its application. The simulation result shows high frequency bandwidth of 17.5 GHz to 57 GHz, 15.9 dB maximum voltage gain, better than -10 dB input matching, and less than 3 dB noise figure. This research also proposes a compact wideband first-order phase shifter (FOPS) and active-only FOPS (AOFOPS). Simulation results demonstrate the FOPS has a tunable pole frequency range between 1.913 GHz and 40.2 GHz, input and output voltage noises of 4.402 nV/VHz and 4.414 nV/VH z respectively, and power dissipation of 0.4862 mW. The AOFOPS circuit also offers a wide tunable range of pole frequency between 34.2 GHz to 56.4 GHz with input noise and output noise of 6.822 nV/VHz and 6.761 nV/VHz respectively, and power dissipation of only 0.0338 mW. The AOFOPS dissipates 12.40 times less power in comparison to state-of-art FOPS circuits. This work also proposes active-only second-order phase shifter. The proposed circuit provides a tunable pole frequency between 16.2 GHz to 42.5 GHz, with input and output noises of 21.698 nV/VHz and 21.593 nV/VHz respectively, while consuming 0.2256 mW power. All circuit performances are verified through HSPICE simulation by utilizing the Stanford CNTFET model at 16 nm technology node with supply voltage of 0.7 V

Development of turnable and miniature microwave filters for modern wireless communication

Due to the increasing demand for new wireless services and applications, the high level of integration and the coexistence of multi-standard (MS) or multi-band operations into a single device are becoming defining trends in designing microwave filters. This has driven considerable technological advances in reconfigurable/tunable and miniaturized filters. More specifically, reconfigurable/tunable filters that tune to different frequency bands instead of classical filter banks have great potential to significantly reduce the system size and complexity; while reducing the filter size becomes essential to achieve the highest degree of integration density in compact and portable wireless devices. In the light of this scenario, the objective of this dissertation is to develop the new design technologies, concepts and filtering configurations for tunable microstrip filters and compact passive microwave filters. To this aim, this dissertation is divided into two main parts. The first part (Part I) focuses on the designs of novel varactor-tuned microstrip filters with advanced performances. In this aspect, new topologies for realizing tunable lowpass and highpass filters are firstly developed. State-of-the-art performances, including wide tuning range, high selectivity with multiple transmission zeros, low insertion loss and compact size for all the tuning states are obtained in both of these filters. Secondly, two novel classes of tunable bandpass filters are presented. One of them is designed based on varactor-loaded parallel-coupled microstrip lines (PCML) and short-circuited stubs, which allows the lower passband edge together with two transmission zeros located around the lower passband skirt to be reconfigured separately. While the other tunable bandpass filter is iii constructed by the combination of tunable bandpass and lowpass filters, featuring both centre frequency and bandwidth tunabilities, as well as high selectivity with abundant transmission zeros. Furthermore, a new concept of tunable lossy filter is demonstrated, which attempts to achieve an equivalent high-Q tunable performance by using low-Q resonators. This concept makes the presented tunable combline filter interesting for some frequency-agile applications in which the low in-band loss variation and high selectivity are much desired while the absolute insertion loss can be a tradeoff. The second part (Part II) is devoted to the design of miniaturized passive microwave filters with improved characteristics. For this, the concept of artificial right-handed and left-handed transmission lines are applied to the signal interference filtering topology, which results in a compact circuit size and good out-of-band performance. In particular, for a further size reduction, such filter is implemented in the forms of multilayered structure by using liquid crystal polymer (LCP) technology. Additionally, another two types of miniaturized bandpass filters using stepped impedance resonators are demonstrated, which are implemented based on different fabrication processes (i.e. LCP bonded multilayer PCB technology and a standard planar PCB technology). Among their main features, the compact size, wide passband, broad stopband with multiple transmission zeros and circuit simplicity are highlighted. For all the proposed design techniques and filtering structures, exhaustive theoretical analyses are done, and design equations and guide rules are provided. Furthermore, all the proposed schemes and/or ideas have been experimentally validated through the design, implementation and measurement of different filters. The fabrication processes of multilayer technology utilized: liquid crystal polymer (LCP) technology and liquid crystal polymer (LCP) bonded multilayer printed circuit board (PCB) technology, are also demonstrated for reference. All of the results achieved in this dissertation make the proposed filters very attractive for their use in modern wireless communication systems.MultiWaves Project (PIRSES-GA-2010-247532) of the Seventh Framework Programme (FP7), European Commission

Development of tunable and miniature microwave filters for modern wireless communications

Due to the increasing demand for new wireless services and applications, the high level of integration and the coexistence of multi-standard (MS) or multi-band operations into a single device are becoming defining trends in designing microwave filters. This has driven considerable technological advances in reconfigurable/tunable and miniaturized filters. More specifically, reconfigurable/tunable filters that tune to different frequency bands instead of classical filter banks have great potential to significantly reduce the system size and complexity; while reducing the filter size becomes essential to achieve the highest degree of integration density in compact and portable wireless devices. In the light of this scenario, the objective of this dissertation is to develop the new design technologies, concepts and filtering configurations for tunable microstrip filters and compact passive microwave filters. To this aim, this dissertation is divided into two main parts. The first part (Part I) focuses on the designs of novel varactor-tuned microstrip filters with advanced performances. In this aspect, new topologies for realizing tunable lowpass and highpass filters are firstly developed. State-of-the-art performances, including wide tuning range, high selectivity with multiple transmission zeros, low insertion loss and compact size for all the tuning states are obtained in both of these filters. Secondly, two novel classes of tunable bandpass filters are presented. One of them is designed based on varactor-loaded parallel-coupled microstrip lines (PCML) and short-circuited stubs, which allows the lower passband edge together with two transmission zeros located around the lower passband skirt to be reconfigured separately. While the other tunable bandpass filter is constructed by the combination of tunable bandpass and lowpass filters, featuring both centre frequency and bandwidth tunabilities, as well as high selectivity with abundant transmission zeros. Furthermore, a new concept of tunable lossy filter is demonstrated, which attempts to achieve an equivalent high-Q tunable performance by using low-Q resonators. This concept makes the presented tunable combline filter interesting for some frequency-agile applications in which the low in-band loss variation and high selectivity are much desired while the absolute insertion loss can be a tradeoff. The second part (Part II) is devoted to the design of miniaturized passive microwave filters with improved characteristics. For this, the concept of artificial right-handed and left-handed transmission lines are applied to the signal interference filtering topology, which results in a compact circuit size and good out-of-band performance. In particular, for a further size reduction, such filter is implemented in the forms of multilayered structure by using liquid crystal polymer (LCP) technology. Additionally, another two types of miniaturized bandpass filters using stepped impedance resonators are demonstrated, which are implemented based on different fabrication processes (i.e. LCP bonded multilayer PCB technology and a standard planar PCB technology). Among their main features, the compact size, wide passband, broad stopband with multiple transmission zeros and circuit simplicity are highlighted. For all the proposed design techniques and filtering structures, exhaustive theoretical analyses are done, and design equations and guide rules are provided. Furthermore, all the proposed schemes and/or ideas have been experimentally validated through the design, implementation and measurement of different filters. The fabrication processes of multilayer technology utilized: liquid crystal polymer (LCP) technology and liquid crystal polymer (LCP) bonded multilayer printed circuit board (PCB) technology, are also demonstrated for reference. All of the results achieved in this dissertation make the proposed filters very attractive for their use in modern wireless communication systems

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Switchable wideband receiver frontend for 5G and satellite applications

Modern day communication architectures provides the requirement for interconnected devices offering very high data rate (more than 10 Gbps), low latency, and support for multiple service integration across existing communication generations with wideband spectrum coverage. An integrated satellite and 5G architecture switchable receiver frontend is presented in this thesis, consisting of a single pole double throw (SPDT) switch and two low noise amplifiers (LNAs) spanning X-band and K/Ka-band frequencies. The independent X-band LNA (8-12 GHz) has a gain of 38 dB at a centre design frequency of 9.8 GHz, while the K/Ka-band (23-28 GHz) has a gain of 29 GHz at a centre design frequency of 25.4 GHz. Both LNAs are a three-stage cascaded design with separated gate and drain lines for each transistor stage. The broadband high isolation single pole double throw (SPDT) switch based on a 0.15 μm gate length Indium Gallium Arsenide (InGaAs) pseudomorphic high electron transistor (pHEMT) is designed to operate at the frequency range of DC-50 GHz with less than 3 dB insertion loss and more than 40 dB isolation. The switch is designed to improve the overall stability of the system and the gain. A gain of about 25 dB is achieved at 9.8 GHz when the X-band arm is turned on and the K/Ka-band is turned off. A gain of about 23 dB is achieved at 25.4 GHz when the K/Ka-band arm is turned on and the X-band arm is off. This presented switchable receiver frontend is suitable for radar applications, 5G mobile applications, and future broadband receivers in the millimetre wave frequency range

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

Enhancing Digital Controllability in Wideband RF Transceiver Front-Ends for FTTx Applications

Enhancing the digital controllability of wideband RF transceiver front-ends helps in widening the range of operating conditions and applications in which such systems can be employed. Technology limitations and design challenges often constrain the extensive adoption of digital controllability in RF front-ends. This work focuses on three major aspects associated with the design and implementation of a digitally controllable RF transceiver front-end for enhanced digital control. Firstly, the influence of the choice of semiconductor technology for a system-on-chip integration of digital gain control circuits are investigated. The digital control of gain is achieved by utilizing step attenuators that consist of cascaded switched attenuation stages. A design methodology is presented to evaluate the influence of the chosen technology on the performance of the three conventionally used switched attenuator topologies for desired attenuation levels, and the constraints that the technology suitable for high amplification places on the attenuator performance are examined. Secondly, a novel approach to the integrated implementation of gain slope equalization is presented, and the suitability of the proposed approach for integration within the RF front-end is verified. Thirdly, a sensitivity-aware implementation of a peak power detector is presented. The increased employment of digital gain control also increases the requirements on the sensitivity of the power detector employed for adaptive power and gain control. The design, implementation, and measurement results of a state-of-the-art wideband power detector with high sensitivity and large dynamic range are presented. The design is optimized to provide a large offset cancellation range, and the influence of offset cancellation circuits on the sensitivity of the power detector is studied. Moreover, design considerations for high sensitivity performance of the power detector are investigated, and the noise contributions from individual sub-circuits are evaluated. Finally, a wideband RF transceiver front-end is realized using a commercially available SiGe BiCMOS technology to demonstrate the enhancements in the digital controllability of the system. The RF front-end has a bandwidth of 500 MHz to 2.5 GHz, an input dynamic range of 20 dB, a digital gain control range larger than 30 dB, a digital gain slope equalization range from 1.49 dB/GHz to 3.78 dB/GHz, and employs a power detector with a sensitivity of -56 dBm and dynamic range of 64 dB. The digital control in the RF front-end is implemented using an on-chip serial-parallel-interface (SPI) that is controlled by an external micro-controller. A prototype implementation of the RF front-end system is presented as part of an RFIC intended for use in optical transceiver modules for fiber-to-the-x applications

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date