5,604 research outputs found
A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C
An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2
An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder
This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C
Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier
This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator
An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC
Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that
1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes,
2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs,
3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers,
4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications,
5. utilizes a standard CMOS process, to lower manufacturing costs, and
6. is integrated, to consume less board space
has been proposed.
The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC.
The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma
A 1.8-V 4-ppm oC Reference Current with Process and Temperature
[[abstract]]A current reference generator with a proposed compensation circuit against temperature variation is presented. The current reference generator provides a reference current of 10 uA with temperature coefficient (TC) of 4 ppm/°C under temperature range from -40 to 125°C. The circuit occupies 0.008 mm2 in a 180-nm standard CMOS process.[[conferencetype]]國際[[conferencedate]]20130630~20130703[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Yeosu, Kore
CMOS analog-digital circuit components for low power applications
Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction
circuits for energy harvester.
The main contribution of this work is the realization of low power consumption and
high efficient circuit components employable in a management circuit for piezoelectricbased
energy harvester. This thesis focuses on the development of current references and
operational amplifiers addressing low power demands. A brief literature review is conducted
on the components necessary for the power extraction circuit, including introduction to
CMOS technology design and research of known low power circuits. It is presented with
multiple implementations for voltage and current references, as well for operational amplifier
designs.
A self-biased current reference, capable of driving the remaining harvesting circuit, is
designed and verified. A novel operational amplifier is proposed by the use of a minimum
current selector circuit topology. It is a three-stage amplifier with an AB class output stage,
comprised by a translinear circuit. The circuit is designed, taking into consideration noise
reduction. The circuit components are designed based on the 0.35mm CMOS technology.
A physical layout is developed for fabrication purposes. This technology was chosen with
consideration of robustness, costliness and performance. The current reference is capable of
outputting a stable 12nA current, which may remain stable in a broad range of power supply
voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at
voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW,
with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de
muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração
de energia com base num elemento piezoelétrico.
Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um
amplificador operacional com baixa exigência de consumo. Uma revisão da literatura
é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor
(CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações
de referência de tensão e corrente são consideradas, e amplificadores operacionais também.
Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e
verificada. Um amplificador operacional original é proposto com uma topologia de seleção
de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída
de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na
sua implementação.
Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi
também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em
conta o seu custo versus desempenho.
A referência de corrente produz uma corrente de 12nA, permanecendo estável para
tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um
coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de
alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima
mantida no estágio de saída
On the design and characterization of femtoampere current-mode circuits
In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is Implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-μm three-metal two-poly standard CMOS process.Ministerio de Ciencia y Tecnología TIC-1999-0446-C02-02, FIT-070000-2001-0859, TIC-2000-0406-P4-05, TIC-2002-10878-EEuropean Union IST-2001-3412
Development and test results of a readout chip for the GERDA experiment
This paper describes the F-CSA104 architecture and its measurement results. The F-CSA104 is for γ spectroscopy with Ge detectors. It is a low noise, fully integrated, four channel XFAB 0.6μm CMOS technology ASIC, that has been developed for the GERDA experiment. Each channel contains a charge sensitive preamplifier (CSA) followed by a 11.7MHz differential line driver. It has been particularly designed to operate in liquid argon (T = 87K/-186°C) and to have a measuring sensitivity of 660e- with an ENC of 110e-, after offline filtering with 10μs shaping, when connected to a 30pF load. Special techniques are used to improve the SNR such as a large input PMOS FET, an integrated 500MΩ CSA feedback resistor and a noise degeneration drain resistor
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