1,427 research outputs found
Modeling and Simulation of Negative Capacitance MOSFETs
The current and voltage characteristics of a MOSFET device are maily characterized by the source
to channel barrier which is controlled by the gate voltage. The Boltazmann statistics which govern
the number of carriers that are able to cross the barrier indicates that to increase the current by a
decade, atleast 60 mV of rise in gate voltage is required. As a result of this limitation, the threshold
voltage of modern MOSFETs cannot be less than about 0.3 V for an ION to IOFF ratio of 5 decades.
This has put a fundamental bottleneck in voltage downscaling increasing the power consumption in
modern IC based chips with billions of transistors.
Sayeef Salahuddin and Supriyo Dutta proposed the idea of including ferroelectric in MOSFET
gate stack which allows an internal voltage ampli�cation at the MOSFET channel which can be used
to achieve a smaller subthreshold swing which would further reduce the power consumption of the
devices. In this thesis we have undertaken a simulation based study of such devices to study how
the inclusion of negative capacitance ferroelectrics leads changes in various device characteristics.
Initially we have taken a compact modeling based approach to study device characteristics in
latest industry standard FinFET devices. For this purpose we have used the BSIM-CMG Verilog A
model and modi�ed the model appropriately to include the e�ect of negative capacitance ferroelectric
in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can
indeed give a subthreshold swing lesser than 60 mV/dec. Further other interesting properties like
negative output resistance and drain induced barrier rising are observed.
Using the compact models developed above, we have analyzed some simple circuits with NC
devices. Initially an inverter shows a hysteresis in the transfer characteristics. This can be attributed
to negative di�erential resistance. Ring oscillator analysis shows that RO frequency for NC devices
is lesser than that of regular devices due to enhanced gate capacitance and slower response of
ferroelectrics.
Scaling analysis has been performed to see the performance of NC devices in future technologies.
For this we used TCAD analysis coupled with Landau Khalatnikov equation. This analysis shows
that NC devices are more e�ective in suppressing short channel e�ects like DIBL and can hence be
used for further downscaling of the devices.
Finally we develop models to take into account the multidomain Landau equations for ferroelec-
tric into account. We have performed such an analysis for a ferroelectric resistor series network. A
similar analysis is performed for short channel double gate MOSFET without inter layer metal be-
tween ferroelectric and the internal MOS device. This analysis showed that coupling factor between
ferroelectric domains plays an important role in the device characteristics
NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance
NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hocresistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale
Overview of carbon-based circuits and systems
This paper presents an overview of the state of the
art on carbon-based circuits and systems made up of carbon
nanotubes and graphene transistors. A tutorial description of
the most important devices and their potential benefits and limitations
is given, trying to identify their suitability to implement
analog and digital circuits and systems. Main electrical models
reported so far for the design of carbon-based field-effect devices
are surveyed, and the main sizing parameters required to implement
such devices in practical integrated circuits are analyzed.
The solutions proposed by cutting-edge integrated circuits and
devices are discussed, identifying current trends, challenges and
opportunities for the circuits and systems community1
Modeling and simulation of graphene field effect transistor (GFET)
Graphene based top-gated Field effect transistor (GFET) is designed and simulated using the device simulator packages. The paper describes fabrication process and the device simulation aspects of the GFET device. Two devices with different gate lengths of 200nm and 350nm are simulated. Device simulations are carried out in open source TCAD software package. The results indicate a depletion FET type operation in which ON/OFF current ratio of 2.25 is obtained
Nanowire electron scattering spectroscopy
Methods and devices for spectroscopic identification of molecules using nanoscale wires are disclosed. According to one of the methods, nanoscale wires are provided, electrons are injected into the nanoscale wire; and inelastic electron scattering is measured via excitation of low-lying vibrational energy levels of molecules bound to the nanoscale wire
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