A Technology Aware Magnetic QCA NCL-HDL Architecture

Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised "snake-clock", we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention Logic (NCL) implementation for the magnetic case so that the "layout=timing" problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture descriptio

Implementation of Binary to Gray Code Converters in Quantum Dot Cellular Automata

Quantum dot cellular automaton (QCA) are dominant nanotechnology which has been used extensively in digital circuits and systems. It is a promising alternative to complementary metal–oxide–semiconductor (CMOS) technology with many enticing features such as high-speed, low power consumption and higher switching frequency than transistor based technology. The code converters are the basic unit for transformation of data to execute arithmetic processes. In this paper, QCA based 2-bit binary-to- gray; 3-bit binary-to-gray and 4-bit binary-to-gray code converter have been proposed. The proposed design reduces the number of cells, area and raises switching speed. The simulations are completed using QCADesigner and Microwindlite tool which is widely used for simulation and verification

Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magneti

Fault Tolerance in Cellular Automata at High Fault Rates

A commonly used model for fault-tolerant computation is that of cellular automata. The essential difficulty of fault-tolerant computation is present in the special case of simply remembering a bit in the presence of faults, and that is the case we treat in this paper. We are concerned with the degree (the number of neighboring cells on which the state transition function depends) needed to achieve fault tolerance when the fault rate is high (nearly 1/2). We consider both the traditional transient fault model (where faults occur independently in time and space) and a recently introduced combined fault model which also includes manufacturing faults (which occur independently in space, but which affect cells for all time). We also consider both a purely probabilistic fault model (in which the states of cells are perturbed at exactly the fault rate) and an adversarial model (in which the occurrence of a fault gives control of the state to an omniscient adversary). We show that there are cellular automata that can tolerate a fault rate $1/2 - \xi$ (with $\xi>0$) with degree $O((1/\xi^2)\log(1/\xi))$, even with adversarial combined faults. The simplest such automata are based on infinite regular trees, but our results also apply to other structures (such as hyperbolic tessellations) that contain infinite regular trees. We also obtain a lower bound of $\Omega(1/\xi^2)$, even with purely probabilistic transient faults only

The LFSR and BCA VHDL Models for Built-in Self-test Circuits

The various test structures are proposed for BIST techniques [1], [2]. A typical structure used for generation of pseudo-random test sets is the linear feedback shift register (LFSR). The BIST techniques have wide application in testing whole devices and embedded components. We focus on the analysis of the state coverage, fault coverage, and optimal structure of BIST schemes

Electrically reconfigurable logic array

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices