Pseudo-random Aloha for Enhanced Collision-recovery in RFID

In this letter we motivate the need to revisit the MAC protocol used in Gen2 RFID system in order to leverage receiver structures with Collision Recovery capabilities at the PHY layer. To this end we propose to consider a simple variant of the Framed Slotted Aloha with pseudo-random (deterministic) slot selection as opposite to the classical random selection. Pseudo-random access allows naturally to implement Inter-frame Successive Interference Cancellation (ISIC) without changing the PHY modulation and coding format of legacy RFID standard. By means of simulations we show that ISIC can bring 20-25% gain in throughput with respect to traditional intra-frame SIC. Besides that, we elaborate on the potential of leveraging pseudo-random access protocols in combination with advanced PHY techniques in the context of RFID applications.Comment: This manuscript has been submitted to IEEE on the 19th September 201

ISI Cancellation Using Blind Equalizer Based on DBC Model for MIMO-RFID Reader Reception

Under the dyadic backscatter channel (DBC) model, a conventional zero forcing (ZF) and minimum mean square error (MMSE) method for MIMO-RFID reader reception are not able to be rapidly cancelled inter-symbol interference (ISI) because of the error of postpreamble transmission. In order to achieve the ISI cancellation, the conventional method of ZF and MMSE are proposed to resolve a convergence rate without postpreamble by using a constant modulus algorithm (CMA). Depending on the cost function, the CMA is used which based on second order statistics to estimate the channel statement of channel transfer function. Furthermore, the multiple-tag detection is also considered under the assumption of the maximum likelihood estimation. The comparison of the conventional method and the proposed method is analyzed by using computer simulation and experimental data. We can see that the proposed method is better than the conventional method with a faster ISI cancelling and a lower bit error rate (BER) improving as up to 12 tags

Towards Extended Bit Tracking for Scalable and Robust RFID Tag Identification Systems

The surge in demand for Internet of Things (IoT) systems and applications has motivated a paradigm shift in the development of viable radio frequency identification technology (RFID)-based solutions for ubiquitous real-Time monitoring and tracking. Bit tracking-based anti-collision algorithms have attracted considerable attention, recently, due to its positive impact on decreasing the identification time. We aim to extend bit tracking to work effectively over erroneous channels and scalable multi RFID readers systems. Towards this objective, we extend the bit tracking technique along two dimensions. First, we introduce and evaluate a type of bit errors that appears only in bit tracking-based anti-collision algorithms called false collided bit error in single reader RFID systems. A false collided bit error occurs when a reader perceives a bit sent by tag as an erroneous bit due to channel imperfection and not because of a physical collision. This phenomenon results in a significant increase in the identification delay. We introduce a novel, zero overhead algorithm called false collided bit error selective recovery tackling the error. There is a repetition gain in bit tracking-based anti-collision algorithms due to their nature, which can be utilized to detect and correct false collided bit errors without adding extra coding bits. Second, we extend bit tracking to 'error-free' scalable mutli-reader systems, while leaving the study of multi-readers tag identification over imperfect channels for future work. We propose the multi-reader RFID tag identification using bit tracking (MRTI-BT) algorithm which allows concurrent tag identification, by neighboring RFID readers, as opposed to time-consuming scheduling. MRTI-BT identifies tags exclusive to different RFIDs, concurrently. The concept of bit tracking and the proposed parallel identification property are leveraged to reduce the identification time compared to the state-of-The-Art. 2013 IEEE.This work was supported by the Qatar National Research Fund (a member of Qatar Foundation) through NPRP under Grant 7-684-1-127. The work of A. Fahim and T. ElBatt was supported by the Vodafone Egypt Foundation.Scopu

A New Algorithm for Solving Ring-LPN with a Reducible Polynomial

The LPN (Learning Parity with Noise) problem has recently proved to be of great importance in cryptology. A special and very useful case is the RING-LPN problem, which typically provides improved efficiency in the constructed cryptographic primitive. We present a new algorithm for solving the RING-LPN problem in the case when the polynomial used is reducible. It greatly outperforms previous algorithms for solving this problem. Using the algorithm, we can break the Lapin authentication protocol for the proposed instance using a reducible polynomial, in about 2^70 bit operations

Cross-Sender Bit-Mixing Coding

Scheduling to avoid packet collisions is a long-standing challenge in networking, and has become even trickier in wireless networks with multiple senders and multiple receivers. In fact, researchers have proved that even {\em perfect} scheduling can only achieve $\mathbf{R} = O(\frac{1}{\ln N})$. Here $N$ is the number of nodes in the network, and $\mathbf{R}$ is the {\em medium utilization rate}. Ideally, one would hope to achieve $\mathbf{R} = \Theta(1)$, while avoiding all the complexities in scheduling. To this end, this paper proposes {\em cross-sender bit-mixing coding} ({\em BMC}), which does not rely on scheduling. Instead, users transmit simultaneously on suitably-chosen slots, and the amount of overlap in different user's slots is controlled via coding. We prove that in all possible network topologies, using BMC enables us to achieve $\mathbf{R}=\Theta(1)$. We also prove that the space and time complexities of BMC encoding/decoding are all low-order polynomials.Comment: Published in the International Conference on Information Processing in Sensor Networks (IPSN), 201

Adiabatic Approach for Low-Power Passive Near Field Communication Systems

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches

Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data

We provide formal definitions and efficient secure techniques for - turning noisy information into keys usable for any cryptographic application, and, in particular, - reliably and securely authenticating biometric data. Our techniques apply not just to biometric information, but to any keying material that, unlike traditional cryptographic keys, is (1) not reproducible precisely and (2) not distributed uniformly. We propose two primitives: a "fuzzy extractor" reliably extracts nearly uniform randomness R from its input; the extraction is error-tolerant in the sense that R will be the same even if the input changes, as long as it remains reasonably close to the original. Thus, R can be used as a key in a cryptographic application. A "secure sketch" produces public information about its input w that does not reveal w, and yet allows exact recovery of w given another value that is close to w. Thus, it can be used to reliably reproduce error-prone biometric inputs without incurring the security risk inherent in storing them. We define the primitives to be both formally secure and versatile, generalizing much prior work. In addition, we provide nearly optimal constructions of both primitives for various measures of ``closeness'' of input data, such as Hamming distance, edit distance, and set difference.Comment: 47 pp., 3 figures. Prelim. version in Eurocrypt 2004, Springer LNCS 3027, pp. 523-540. Differences from version 3: minor edits for grammar, clarity, and typo

An extra dimension in protein tagging by quantifying universal proteotypic peptides using targeted proteomics

The use of protein tagging to facilitate detailed characterization of target proteins has not only revolutionized cell biology, but also enabled biochemical analysis through efficient recovery of the protein complexes wherein the tagged proteins reside. The endogenous use of these tags for detailed protein characterization is widespread in lower organisms that allow for efficient homologous recombination. With the recent advances in genome engineering, tagging of endogenous proteins is now within reach for most experimental systems, including mammalian cell lines cultures. In this work, we describe the selection of peptides with ideal mass spectrometry characteristics for use in quantification of tagged proteins using targeted proteomics. We mined the proteome of the hyperthermophile Pyrococcus furiosus to obtain two peptides that are unique in the proteomes of all known model organisms (proteotypic) and allow sensitive quantification of target proteins in a complex background. By combining these 'Proteotypic peptides for Quantification by SRM' (PQS peptides) with epitope tags, we demonstrate their use in co-immunoprecipitation experiments upon transfection of protein pairs, or after introduction of these tags in the endogenous proteins through genome engineering. Endogenous protein tagging for absolute quantification provides a powerful extra dimension to protein analysis, allowing the detailed characterization of endogenous proteins

A Tutorial on Clique Problems in Communications and Signal Processing

Since its first use by Euler on the problem of the seven bridges of K\"onigsberg, graph theory has shown excellent abilities in solving and unveiling the properties of multiple discrete optimization problems. The study of the structure of some integer programs reveals equivalence with graph theory problems making a large body of the literature readily available for solving and characterizing the complexity of these problems. This tutorial presents a framework for utilizing a particular graph theory problem, known as the clique problem, for solving communications and signal processing problems. In particular, the paper aims to illustrate the structural properties of integer programs that can be formulated as clique problems through multiple examples in communications and signal processing. To that end, the first part of the tutorial provides various optimal and heuristic solutions for the maximum clique, maximum weight clique, and $k$-clique problems. The tutorial, further, illustrates the use of the clique formulation through numerous contemporary examples in communications and signal processing, mainly in maximum access for non-orthogonal multiple access networks, throughput maximization using index and instantly decodable network coding, collision-free radio frequency identification networks, and resource allocation in cloud-radio access networks. Finally, the tutorial sheds light on the recent advances of such applications, and provides technical insights on ways of dealing with mixed discrete-continuous optimization problems