Processing circuit with asymmetry corrector and convolutional encoder for digital data

A processing circuit is provided for correcting for input parameter variations, such as data and clock signal symmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit. The corrector circuit further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit so that encoded data may be furnished to a modulator at a high data rate for transmission

Automatic control of clock duty cycle

In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops

PCM magnetic tape system efficiently records and reproduces data

Split-phase PCM technique consists of data and clock signal recording and reproduction systems. This PCM magnetic tape system achieves a high packing density on the tape and provides a symmetrical reproduction of the recorded signal

Complementary MOS four-phase logic circuits

Technique can provide four-phase clock signal from single-phase clock and requires only one power supply voltage. This arrangement saves considerable power compared to circuits having load resistor between power supply and ground

Synchronizer for random binary data

Simplified binary-data transition detector, for synchronization of relatively noise-free signals, can be used with radio or cable data-control links. It permits reception of binary data in absence of clock signal or self-clocking coder

0.75 atoms improve the clock signal of 10,000 atoms

Since the pioneering work of Ramsey, atom interferometers are employed for precision metrology, in particular to measure time and to realize the second. In a classical interferometer, an ensemble of atoms is prepared in one of the two input states, whereas the second one is left empty. In this case, the vacuum noise restricts the precision of the interferometer to the standard quantum limit (SQL). Here, we propose and experimentally demonstrate a novel clock configuration that surpasses the SQL by squeezing the vacuum in the empty input state. We create a squeezed vacuum state containing an average of 0.75 atoms to improve the clock sensitivity of 10,000 atoms by 2.05 dB. The SQL poses a significant limitation for today's microwave fountain clocks, which serve as the main time reference. We evaluate the major technical limitations and challenges for devising a next generation of fountain clocks based on atomic squeezed vacuum.Comment: 9 pages, 6 figure

Digital numerically controlled oscillator

The frequency and phase of an output signal from an oscillator circuit are controlled with accuracy by a digital input word. Positive and negative alterations in output frequency are both provided for by translating all values of input words so that they are positive. The oscillator reference frequency is corrected only in one direction, by adding phase to the output frequency of the oscillator. The input control word is translated to a single algebraic sign and the digital 1 is added thereto. The translated input control word is then accumulated. A reference clock signal having a frequency at an integer multiple of the desired frequency of the output signal is generated. The accumulated control word is then compared with a threshold level. The output signal is adjusted in a single direction by dividing the frequency of the reference clock signal by a first integer or by an integer different from the first integer

Dynamically Altering Clock Signal Frequencies in LTPO AMOLED Displays

This publication describes systems and techniques for dynamically altering clock signal frequencies in low-temperature polysilicon metal oxide (LTPO) active-matrix organic light-emitting diode (AMOLED) displays. In an aspect, a display manager may identify a refresh rate implemented by an operating system of an electronic device, as well as a use case enacted by a user. As a result of the identification, the display manager can implement a suitable clock signal frequency for self-refresh operations. By dynamically altering clock signal frequencies, the display manager can reduce the number of transactions (e.g., passing high signals, passing low signals) in display panel circuitry associated with self-refresh operations. In so doing, the display manager can dynamically alter clock signal frequencies in LTPO AMOLED displays to reduce power consumption without degrading user experience