Benchmarking for high-level synthesis

This paper discusses issues in benchmarking for synthesis, and suggests techniques for the comparison of benchmark descriptions, the synthesis tools used, as well as the synthesized designs finally generated. We propose a classification scheme for the assumptions made for the comparison of different synthesis tools, and present an Assumptions Chart that can be used to visualize different benchmarks, tools and synthesis results. We illustrate application of this Assumptions Chart using synthesis experiments that were conducted on some sample High-Level Synthesis Workshop bench-marks

Comparision of Different Logic style for High Performance Wave Pipeline Circuit

High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications .Existing logic families cannot provide both of them simultaneously. We propose Double Pass Transistor Logic (DPL) which can be used as a universal logic to provide finest grain pipelining without affecting overall latency or increasing the area. It  does not require  any special process steps and hence, can be  realized  in  a  normal process  technology  as  against  the CPL proposed  by  Yano et  al  [2] which uses  threshold  voltage  adjustment  of  selected  devices.  The design procedure is described for (a) low latency, (b) high throughput and (c) low area requirements. In  addition to the various  advantages,  it  is envisioned  that DPL  designs  can also be used to build ultra-high speed  pipelined system without pipelining latches, viz., wave pipelined  digital systems,  where the throughput achievable  is beyond  that permitted  by  the delay  of  a pipeline stage

Multiple voltage scheme with frequency variation for power minimization of pipelined circuits at high-level synthesis

High-Level Synthesis (HLS) is defined as a translation process from a behavioral description into structural description. The high-level synthesis process consists of three interdependent phases: scheduling, allocation and binDing The order of the three phases varies depending on the design flow. There are three important quality measures used to support design decision, namely size, performance and power consumption. Recently, with the increase in portability, the power consumption has become a very dominant factor in the design of circuits. The aim of low-power high-level synthesis is to schedule operations to minimize switching activity and select low power modules while satisfying timing constraints. This thesis presents a heuristic that helps minimize power consumption by operating the functional units at multiple voltages and varied clock frequencies. The algorithm presented here deals with pipelined operations where multiple instance of the same operation are carried out. The algorithm was implemented using C++, on LINUX platform

A global routing technique for wave-steered design methodology

Wave-Steering is a new circuit design methodology to realize high throughput circuits by embedding layout friendly structures in silicon. Latches guarantee correct signal arrival times at the input of synthesized modules and maintain the high throughput of operation. This paper presents a global routing technique for networks of wave-steered blocks. Latches can be distributed along interconnects. Their number depends on net topologies and signal ordering at the inputs of wave steered blocks. here, we route nets using Steiner tree heuristics and determine signal ordering and latch positions on interconnect. The problem of total latch number minimization is solved using SAT formulation. Experimental results on benchmark circuits show the efficiency of our technique. We achieve on average a 40% latch reduction at minimum latency over un-optimized circuits operating at 250 MHz in 0.25 &#956;m CMOS technology</p

A mathematical formulation of the loop pipelining problem

This paper presents a mathematical model for the loop pipelining problem that considers several parameters for optimization and supports any combination of resource and timing constraints. The unrolling degree of the loop is one of the variables explored by the model. By using Farey’s series, an optimal exploration of the unrolling degree is performed and optimal solutions not considered by other methods are obtained. Finding an optimal schedule that minimizes resource and register requirements is solved by using an Integer linear programming (ILP) model. A novel paradigm called branch and prune is proposed to eficiently converge towards the optimal schedule and prune the search tree for integer solutions, thus drastically reducing the running time. This is the first formulation that combines the unrolling degree of the loop with timing and resource constraints in a mathematical model that guarantees optimal solutions.Peer ReviewedPostprint (author's final draft

Circuit design and analysis for on-FPGA communication systems

On-chip communication system has emerged as a prominently important subject in Very-Large- Scale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes

Minimization Of Power Dissipation In Digital Circuits Using Pipelining And A Study Of Clock Gating Technique

Power dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today\u27s digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount of power dissipation. The concept of pipelining is explained and the reduction in the power dissipation of the multipliers after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is 0.35µm CMOS and the simulator used is SPECTRE S

NIKEL: Electronics and data acquisition for kilopixels kinetic inductance camera

A prototype of digital frequency multiplexing electronics allowing the real time monitoring of microwave kinetic inductance detector (MKIDs) arrays for mm-wave astronomy has been developed. Thanks to the frequency multiplexing, it can monitor simultaneously 400 pixels over a 500 MHz bandwidth and requires only two coaxial cables for instrumenting such a large array. The chosen solution and the performances achieved are presented in this paper.Comment: 21 pages, 14 figure