2,604 research outputs found
Compositional Algorithms for Succinct Safety Games
We study the synthesis of circuits for succinct safety specifications given
in the AIG format. We show how AIG safety specifications can be decomposed
automatically into sub specifications. Then we propose symbolic compositional
algorithms to solve the synthesis problem compositionally starting for the
sub-specifications. We have evaluated the compositional algorithms on a set of
benchmarks including those proposed for the first synthesis competition
organised in 2014 by the Synthesis Workshop affiliated to the CAV conference.
We show that a large number of benchmarks can be decomposed automatically and
solved more efficiently with the compositional algorithms that we propose in
this paper.Comment: In Proceedings SYNT 2015, arXiv:1602.0078
Word-level Symbolic Trajectory Evaluation
Symbolic trajectory evaluation (STE) is a model checking technique that has
been successfully used to verify industrial designs. Existing implementations
of STE, however, reason at the level of bits, allowing signals to take values
in {0, 1, X}. This limits the amount of abstraction that can be achieved, and
presents inherent limitations to scaling. The main contribution of this paper
is to show how much more abstract lattices can be derived automatically from
RTL descriptions, and how a model checker for the general theory of STE
instantiated with such abstract lattices can be implemented in practice. This
gives us the first practical word-level STE engine, called STEWord. Experiments
on a set of designs similar to those used in industry show that STEWord scales
better than word-level BMC and also bit-level STE.Comment: 19 pages, 3 figures, 2 tables, full version of paper in International
Conference on Computer-Aided Verification (CAV) 201
AbsSynthe: abstract synthesis from succinct safety specifications
In this paper, we describe a synthesis algorithm for safety specifications
described as circuits. Our algorithm is based on fixpoint computations,
abstraction and refinement, it uses binary decision diagrams as symbolic data
structure. We evaluate our tool on the benchmarks provided by the organizers of
the synthesis competition organized within the SYNT'14 workshop.Comment: In Proceedings SYNT 2014, arXiv:1407.493
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur
Parallelization of cycle-based logic simulation
Verification of digital circuits by Cycle-based simulation can be performed in parallel. The parallel implementation requires two phases: the compilation phase, that sets up the data needed for the
execution of the simulation, and the simulation phase, that consists in executing the parallel simulation of the considered circuit for a certain number of cycles. During the early phase of design, compilation phase has to be repeated each time a bug is found. Thus, if the time of the compilation phase is too high, the advantages stemming from the parallel approach may be lost. In this work we propose an
effective version of the compilation phase and compute the corresponding execution time. We also analyze the percentage of execution time required by the different steps of the compilation phase for
a set of literature benchmarks. Further, we implemented the simulation phase exploiting the GPU architecture, and we computed the execution times for a set of benchmarks obtaining values comparable
with literature ones. Finally, we implemented the sequential version of the Cycle-based simulation in such a way that the execution time is optimized. We used the sequential values to compute the speedup
of the parallel version for the considered set of benchmarks
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