Dispersion measurements of fiber-optic components and applications of a novel tunable filter for optical communications

Optical communications has experienced a rapid development during the last decade. More bandwidth can be acquired by decreasing the spacing of the optical channels or by increasing the data rate. Characterization of the optical components and active monitoring of the network calls for accurate measurement methods. The objective of this thesis is to investigate and develop measurement methods and instruments for measuring important parameters of the components used in optical communications. Chromatic dispersion of optical fibers and frequency chirp of the laser transmitters set limits for the data rate and transmission distance. Measurements of dispersion have traditionally been performed using a phase-shift method. When high modulation frequencies are applied to achieve high resolution an error could be introduced. In this thesis, the measurement accuracy of this method is analyzed in detail and a novel method for estimating the accuracy and correcting the measurement result is developed. A Fabry-Perot interferometer finds numerous applications in many fields of optics. In this thesis, tunable Fabry-Perot etalon filters made of silicon were developed and several applications for these devices are demonstrated. A new device for measurements of time-resolved frequency chirp of directly modulated laser diodes in real time is developed. Interaction between the dispersion and frequency chirp limits the use of directly modulated lasers in long-haul optical links. Another application is monitoring of the wavelength of optical transmitters. The wavelength of the laser diode may shift due to aging and active monitoring and controlling of the wavelength is required. In addition, the filter improves the performance of the directly modulated transmitter by temporal reshaping of the pulses. The filter is also applied in reducing the frequency chirp of gain-switched pulses generated with a diode laser. These pulses can then be made transform limited and can for example be used in generation of optical solitons. Finally, the etalon is employed in realization of a compact wavelength reference for calibration of the wavelength scale of the optical spectrum analyzers and wavemeters. The transmission spectrum of the etalon consists of equidistant fringes. Each of these fringes can be applied as an accurate reference over a large wavelength range once the temperature of the filter is stabilized. This reference was developed to be automatic and it has an adequate accuracy for performing calibrations of field instruments.reviewe

SPICE-Based Heat Transport Model for Non-Intrusive Thermal Diagnostic Applications

Nondestructive material testing and diagnostics play an important role in reliability analysis, component wear-out testing, life-cycle estimates, and safety inspections. Of the several techniques available for nondestructive inspections, thermal analysis has been chosen to be the focus of this thesis research. An equivalence between the system of equations for the heat flow problem, and the variables of circuit theory suggests that an electrical model can be constructed to represent the actual thermal system. This electrical model is constructed based upon a finite difference discretization of the heat flow equation. Using these associations a basic one-dimensional electrical model has been constructed and linked with a circuit simulator (such as SPICE) to simulate the transient, steady state and ac heating scenarios of a sample thermal system. The basic model has been proven to accurately represent the thermal system. It has then been expanded to include temperature dependence of the conductivity parameter (with the aid of voltage controlled resistors) and multidimensional heat flow by extending the one-dimensional circuit along various directions. Finally, this SPICE-based model has been applied for thermal analysis of samples containing surface material defects such as cracks. It is shown that the model can adequately locate such cracks based upon the electro-thermal relationships between time delay and voltage (temperature) magnitudes. It would thus be a useful simulation tool in the analysis of defects and for investigating non-intrusive thermal diagnostic response

Fabrication and High Speed Optoelectronic Characterization of Semiconductor Devices

This work is an investigation on the use of high speed optoelectronic techniques for the characterization of semiconductor devices. A low-frequency electrooptic probe station was demonstrated as well as the optoelectronic sampling scheme. The optoelectronic sampling technique relies on fast photoconductive switches for its operation. The autocorrelation signal detected in optoelectronic sampling was compared with signal detection by conventional techniques employing a sampling oscilloscope and a network analyser. The optoelectronic techniques described in this work depend critically on short-pulse lasers for the measurement of high speed devices. A fibre-grating pulse compressor was set-up to shorten the 120 ps pulses produced by a mode-locked Nd:YAG laser. Compression by a factor of 40 was demonstrated and nearly transform limited pulses of 3 ps duration were obtained. However, the output of the pulse compressor is very noisy and the output power is not high enough to enable electrooptic sampling experiments, in a jitter-free scheme. The same Nd:YAG laser was frequency doubled and used to synchronously pump a rhodamine 6G dye laser. Autocorrelation measurements obtained with the dye laser are again, very noisy and with poor reproducibility. The noise problems with the pulse compressor and with the dye laser were traced back to the Nd:YAG pump laser. It is concluded that this laser should be avoided as the source of short pulses for the electrooptic and optoelectronic measurement techniques. The use of a feedback loop is likely to reduce the noise in this laser, but drift in the intensity in a long time scale would still be present. A mode-locked Ti:Sapphire laser was also used for measurements in this project. Autocorrelation measurements taken with this laser are totally reproducible and contain little or no noise. The devices measured in this project were made by a combination of electron-beam lithography and photolithography. The use of these two lithography techniques together was made possible by the design of a mask set with alignment marks which can be used for registration in a mask aligner and in the electron beam lithography machine. Discrete devices were made and characterized by electrical techniques. Fabrication procedures were developed for resistors, Metal-Insulator-Metal (MIM) capacitors and for the Optoelecttonic Sampling Device (OSD). Discrete Mesfets were fabricated on MBE grown epilayers and their I-V characteristics were measured. A simplified optoelectronic sampling device was designed and made in a single lithographic step. It provides a quick way of producing devices in which autocorrelation measurements can be performed to determine the carrier lifetime in the substrate material. The optoelectronic sampling devices were made on four different substrate materials. The first one is a high purity, MBE grown GaAs epilayer, with very long lifetime (2ns). The control samples were made on "standard" semi-insulating GaAs, whose carrier lifetime is ~200 ps. Proton implantation in some of these devices made on SI GaAs substrate was used as a means of shortening the carrier lifetime, to produce fast turn-off times in the photoconductive switches. The lifetime after implantation of 4 x 10e14 protons/cm2 was estimated from an optoelectronic sampling measurement, to be around 40 ps. This is still a very long lifetime for the photoconductive switches. It is thought that self-annealing of the deep electron traps, caused by the lack of temperature control in the implanter, prevented the achievement of short lifetime in the switches. GaAs epilayers were grown by MBE at a temperature around 25

Characterization and Compensation of Thermal Effects in GaN HEMT Technologies

Further advancements with GaN based technologies relies on the ability to handle the heat flux, which consequently arises from the high power density. Advanced cooling techniques and thermal optimization of the technology are therefore prioritized research areas. Characterization techniques play a key role in the development of new cooling solutions, since these rely on accurate measurements of e.g. the temperature of the device. This thesis covers techniques to electrically characterize the lateral and vertical heat properties in GaN, and a temperature compensation technique for GaN MMICs.The first part outlines a methodology to electrically extract the thermal resistance of a GaN resistor without risking distortion from field induced electron trapping effects, which are exhibited by GaN heterostructures. The technique uses differential resistance measurements to identify a suitable resistor geometry, which minimizes trapping effects while enhancing the self-heating. Such conditions are crucial for electrical methods since these exploit the self- heating for a thermal analysis.Furthermore, a test structure and measurement method to electrically characterize the lateral heat spread was designed and evaluated. The structure is implemented with a thermal sensor, which utilizes the temperature-dependent IV characteristics of a GaN resistor, making it suitable for integration in GaN MMICs. The transient response can be obtained to extract the thermal time constants and propagation delay of the heat spread. At higher ambient temperatures, the propagation delay increases and the thermal coupling is increased. Lastly, a biasing technique to compensate for thermal degradation of the RF performance of an LNA was developed. By utilizing the gate- and drain voltage dependence of the RF performance, a constant gain against increasing temperature can e.g. be achieved

Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions

Electrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation. Thermal failure is one of the main reasons to cause device failure under ESD conditions. A compact model is developed to predict thermal failure with circuit simulators. Instead of considering the detailed failure mechanisms, a failure temperature is introduced to indicate device failure. The developed model is implemented by a multiple-stage thermal network. P-N junction is the fundamental structure for ESD protection devices. An enhanced diode model is proposed and is used to simulate the device behaviors for ESD events. The model includes all physical effects for ESD conditions, which are voltage overshoot, self-heating effect, velocity saturation and thermal failure. The proposed model not only can fit the I-V and transient characteristics, but also can predict failure for different pulses. Safe Operating Area (SOA) is an important factor to evaluate the LDMOS performance. The transient SOA boundary is considered as power-defined. By placing the failure monitor under certain conditions, the developed modeling methodology can predict the boundary of transient SOA for any short pulse stress conditions. No matter failure happens before or after snapback phenomenon. Weibull distribution is popular to evaluate the dielectric lifetime for CVS. By using the transformative version of power law, the pulsing stresses are converted into CVS, and TDDB under ESD conditions for SiN MIMCAPs is analyzed. The thickness dependency and area independency of capacitor breakdown voltage is observed, which can be explained by the constant ?E model instead of conventional percolation model

High Temperature Electronics Design for Aero Engine Controls and Health Monitoring

There is a growing desire to install electronic power and control systems in high temperature harsh environments to improve the accuracy of critical measurements, reduce the amount of cabling and to eliminate cooling systems. Typical target applications include electronics for energy exploration, power generation and control systems. Technical topics presented in this book include:• High temperature electronics market• High temperature devices, materials and assembly processes• Design, manufacture and testing of multi-sensor data acquisition system for aero-engine control• Future applications for high temperature electronicsHigh Temperature Electronics Design for Aero Engine Controls and Health Monitoring contains details of state of the art design and manufacture of electronics targeted towards a high temperature aero-engine application. High Temperature Electronics Design for Aero Engine Controls and Health Monitoring is ideal for design, manufacturing and test personnel in the aerospace and other harsh environment industries as well as academic staff and master/research students in electronics engineering, materials science and aerospace engineering

Materials Characterization and Microelectronic Implementation of Metal-insulator Transition Materials and Phase Change Materials

Vanadium dioxide (VO2) is a metal-insulator transition (MIT) material, and germanium telluride (GeTe) is a phase change material (PCM), both of which undergo several orders of magnitude increase in electrical conductivity from room temperature to their transition temperatures. They are candidates for many important technologies, including ultra-fast electronic memory, optical switches and filters, and active layers in terahertz metamaterials, among others. The physical mechanisms causing the phase transitions in these materials are explained and investigated experimentally. These materials were incorporated into six types of microelectronic devices, which were designed, fabricated, and tested at the Air Force Institute of Technology (AFIT). Additionally, these materials were investigated by materials characterization methods spanning the majority of the electromagnetic spectrum. The results show a most suitable applicability to electronic radio frequency (RF) switches, terahertz (THz) modulators, and phase change random access memory (PCRAM). Simple RF switches had 2 dB insertion losses and 30 dB of isolation, THz transmittance modulation of up to 99.5%, and PCRAM cells with threshold electric fields of approximately 1 V/ m

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip