Scalability of broadcast performance in wireless network-on-chip

Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors with hundreds or thousands of cores. The main reason is that the performance of such networks drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.Peer ReviewedPostprint (published version

Frequency Multipliers in SiGe BiCMOS for Local Oscillator Generation in D-band Wireless Transceivers

Communications at millimeter-wave (mm-Wave) have drawn a lot of attention in recent years due to the wide available bandwidth which translates directly to higher data transmission capacity. Generation of the transceivers local oscillation (LO) is critical because many contrasting requirements, i.e. tuning range (TR), phase noise (PN), output power, and level of spurious tones, affect the system performance. Differently from what is commonly pursued at Radio Frequency, LO generation with a PLL embedding a VCO at the desired output frequency is not viable at mm-wave. A more promising approach consists of a PLL in the 10-20GHz range, where silicon VCOs feature the best figure of merit, followed by a frequency multiplier. In this thesis, a frequency multiplication chain is investigated to up-convert an LO signal from X-band to D-band by a multiplication factor of 12. The multiplication is done in steps of 3, 2, and 2. A sextupler chip comprises the tripler and the first doubler and the last doubler stage which upconverts the LO signal from E- to D-band is realized in a separate chip, all in a 55nm SiGe BiCMOS technology. The frequency tripler circuit is based on a novel circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a separate break-out chip and consuming 23mW of DC power, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% fractional bandwidth and robustness to power variation of the driving signal over a 15dB range. Including the E-band doubler, the sextupler chip achieves a peak output power of 1.7dBm at 74.4GHz and remains within 2dB variation from 70GHz to 82GHz, corresponding to 16% fractional BW. In this frequency range, the leakages of all harmonics are suppressed by more than 40dBc. The design of the D-band doubler was aimed at delivering high output power with high efficiency and high conversion gain. Toward this end, the efficiency of a push-push pair was improved by a stacked Colpitts oscillator to boost the power conversion gain by 10dB. Moreover, the common-collector configuration keeps separate the oscillator tank from the load, allowing independent optimization of the harmonic conversion efficiency and the load impedance for maximum power delivery. The measured performance of the test chip demonstrated Pout up to 8dBm at 130GHz with 13dB conversion gain and 6.3% Power Added Efficiency

Millimeter-Wave Reconfigurable CMOS-MEMS Integrated Devices

The millimeter-wave spectrum has sparked interest recently as a promising alternative to meet bandwidth requirements for wireless local area networks, vehicular radars, short-range multi-Gb/s links, and next-generation cellular system communications (5G). The unlicensed 7 GHz ISM band around 60 GHz is of particular interest. Compared to semiconductor technologies, Micro-Electro-Mechanical Systems (MEMS) have the potential to realize reconfigurable millimeter-wave devices with superior performance in terms of linearity, insertion loss and DC power consumption. This thesis presents the development and fabrication of miniaturized, low insertion loss, high isolation RF-MEMS switches implemented in CMOS chips through the use of a post-processing technique. Several CMOS-MEMS switches operating at 60 GHz and 77 GHz are demonstrated. Prototype units for SPST, SP3T switches and a distributed MEMS transmission line (DMTL) network are integrated on CMOS 0.35 μm. The challenges involved in realizing CMOS-MEMS devices at mm-wave frequencies are also addressed in this work

Simulação e projeto de indutores integrados em tecnologia cmos para circuitos de radiofrequência

Orientador : Prof. Bernardo Rego Barros de Almeida LeiteCoorientador : Prof. André Augusto MarianoDissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa: Curitiba, 08/05/2017Inclui referências : f.78-81Resumo: Este trabalho apresenta um passo a passo para qualificar a utilização de simulações eletromagnéticas com a finalidade de prever o comportamento de elementos passivos, especialmente indutores. Três dispositivos foram projetados, medidos e simulados. Tratam-se de dois indutores de duas camadas em que um deles possui uma estrutura de blindagem de substrato e um indutor de apenas uma camada (também com a blindagem). Os três elementos apresentam uma topologia octogonal simétrica. Os elementos são detalhados, bem como suas topologias e parâmetros construtivos. Para a análise individual dos dispositivos, o desacoplamento dos elementos externos é realizado. Figuras de mérito e parâmetros de análise são estabelecidos e utilizados para examinar a operação dos indutores através da comparação entre eles, visando demonstrar o efeito de certos parâmetros de projeto na performance dos elementos. A simulação eletromagnética é analisada através da comparação entre as figuras de mérito obtidas através da medição dos elementos e os dados obtidos pelas simulações. Investigam-se os parâmetros de análise para identificar causas de possíveis discrepâncias entre a simulação e os circuitos medidos. As simulações eletromagnéticas apresentaram resultados próximos às medidas, entretanto, algumas configurações podem ser melhor exploradas, o que poderia levar a melhores resultados. No pior caso, as simulações eletromagnéticas apresentaram uma discrepância de 15,7% no fator de qualidade máximo, 2,3% na frequência de ressonância e 9,9% na indutância de baixa frequência em relação aos dados obtidos da medição. Palavras-Chave: Indutores, Simulações Eletromagnéticas, MicroeletrônicaAbstract: This work presents a step-by-step process to determine the applicability of electromagnetic simulations to predict inductor behavior. Three elements were designed, measured, characterized and simulated. These elements are a shielded double-layered, a shieldless double-layered and a shielded single-layered symmetric inductor. The elements are presented, their topology and constructive parameters are described and their differences are discussed. The devices were measured and the data were adapted as necessary. To evaluate the elements performance (as well as the simulation) analysis parameters are established and detailed. The elements' parameters are compared and discrepancies are highlighted. The performances of these elements are rated according to figures of merit such as equivalent inductance (5.1 nH for the double-layered elements and 5.5 nH for the single-layered), maximum quality factor (11.2 for the shielded double-layered, 12.2 for the shieldless double-layered, and 10.3 for the single-layered inductors) and self-resonant frequency (6.84 GHz, 6.89 GHz, and 8.3 GHz, respectively). The electromagnetic simulation presents results close to measurement; however, exploring not tested configurations could lead to improvements. In the worst presented case, the maximum quality factor displayed a discrepancy of 15.7%, the self-resonant frequency presented a 2.3% discrepancy, and the low frequency inductance showed a 9.9% difference between simulation and measured data. Keywords: Inductors, Electromagnetic Simulations, Microelectronic

Design of wideband silicon-germanium RF front end circuits for broadband communications systems

This thesis discusses the design of wideband front-end circuits for broadband communications systems, designed in silicon-germanium technology. The bandwidths of these circuits cover from 2 GHz to 18 GHz. In Chapter 1, an introduction to wideband communications systems is presented. In addition, a brief summary of phased array radars and the need for wideband radars are discussed. Also, an overview of Silicon-Germanium technology and its advantages in the context of wideband circuit design are discussed. In Chapter 2, the design challenges associated with wideband RF front-end circuits are presented. In particular, the design space of wideband power amplifiers and low-noise amplifiers is discussed. Both the active and passive circuit design difficulties for each circuit are evaluated. In addition, traditional approaches to amplifier design and their drawbacks for wideband circuits are explained. In Chapter 3, the design of a wideband 1-20 GHz Silicon-Germanium power amplifier is discussed. In this design, a distributed amplifier topology is utilized with transistor stacking to simultaneously achieve high output power and wideband impedance matching. This amplifier is designed in a highly scaled 90 nm SiGe BiCMOS process. Measurement results and a comparison to state-of-the-art wideband power amplifiers are shown. This work, ”A 1-20 GHz Distributed, Stacked SiGe Power Amplifier” was published in the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium [1]. In Chapter 4, the design of a wideband 1-18 GHz Silicon-Germanium low noise ampli- fier is presented. A resistive feedback topology is used to achieve wideband operation with moderate gain and low noise figure. In addition, a cryogenic characterization of this amplifier is conducted with measurements of S-parameters, 1 dB compression point, and noise over temperature. A comparison to state-of-the-art cryogenic amplifiers is shown. Furthermore, the demonstration and explanation of an on-wafer cryogenic noise measurement scheme are presented. This work, ”A Low Power, Wideband SiGe Low Noise Amplifier for Cryogenic Temperature Operation” will be submitted to the 2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). In Chapter 5, a summary of the achieved results is shown. In addition, future research directions are discussed.M.S