NASA SBIR abstracts of 1990 phase 1 projects

The research objectives of the 280 projects placed under contract in the National Aeronautics and Space Administration (NASA) 1990 Small Business Innovation Research (SBIR) Phase 1 program are described. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses in response to NASA's 1990 SBIR Phase 1 Program Solicitation. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 280, in order of its appearance in the body of the report. The document also includes Appendixes to provide additional information about the SBIR program and permit cross-reference in the 1990 Phase 1 projects by company name, location by state, principal investigator, NASA field center responsible for management of each project, and NASA contract number

Analysis and modeling methods for predicting functional robustness of integrated circuits during fast transient events

La miniaturisation des circuits intégrés se poursuit de nos jours avec le développement de technologies toujours plus fines et denses. Elle permet une intégration des circuits toujours plus massive, avec des performances plus élevées et une réduction des coûts de production. La réduction de taille des circuits s'accompagne aussi d'une augmentation de leur sensibilité électrique. L'électronique automobile est un acteur majeur dans la nouvelle tendance des véhicules autonomes. Ce type d'application a besoin d'analyser des données et d'appliquer des actions sur le véhicule en temps réel. L'objectif à terme est d'améliorer la sécurité des usagers. Il est donc vital de garantir que ces modules électroniques pourront effectuer leurs tâches correctement malgré toutes les perturbations auxquelles ils seront exposés. Néanmoins, l'environnement automobile est particulièrement sévère pour l'électronique. Parmi tous les stress rencontrés, les décharges électrostatiques (ESD - Electrostatic Discharge) sont une importante source d'agression électrique. Ce type d'évènement très bref est suffisamment violent pour détruire des composants électroniques ou les perturber pendant leur fonctionnement. Les recherches présentées ici se concentrent sur l'analyse des défaillances fonctionnelles. À cause des ESD, des fonctions électroniques peuvent cesser temporairement d'être opérantes. Des méthodes d'analyse et de prédiction sont requises au niveau-circuit intégré afin de détecter des points de faiblesses susceptibles de générer des fautes fonctionnelles pendant l'exposition à un stress électrostatique. Différentes approches ont été proposées dans ce but. Une méthode hiérarchique de modélisation a été mise au point afin d'être capable de reproduire la forme d'onde ESD jusqu'à l'entrée du circuit intégré. Avec cette approche, chaque élément du système est modélisé individuellement puis son modèle ajouté au schéma complet. Un cas d'étude réaliste de défaillance fonctionnelle d'un circuit intégré a été analysé à l'aide d'outils de simulation. Afin d'obtenir plus de données sur cette faute, une puce de test a été développée, contenant des structures de surveillance et de mesure directement intégrées dans la puce. La dernière partie de ce travail de recherche est concentrée sur le développement de méthodes d'analyse dans le but d'identifier efficacement des fautes par simulation. Une des techniques développées consiste à modéliser chaque bloc d'une fonction individuellement puis permet de chaîner ces modèles afin de déterminer la robustesse de la fonction complète. La deuxième méthode tente de construire un modèle équivalent dit boite-noire d'une fonction de haut-niveau d'un circuit intégré. Ces travaux de recherche ont mené à la mise au point de prototypes matériels et logiciels et à la mise en évidence de points bloquants qui pourront constituer une base pour de futurs travaux.Miniaturization of electronic circuits continues nowadays with the more recent technology nodes being applied to diverse fields of application such as automotive. Very dense and small integrated circuits are interesting for economic reasons, because they are cheaper to manufacture in mass and can pack more functionalities with elevated performances. The counterpart of size reduction is integrated circuits becoming more fragile electrically. In the automotive world, the new trend of fully autonomous driving is seeing tremendous progress recently. Autonomous vehicles must take decisions and perform critical actions such as braking or steering the wheel. Those decisions are taken by electronic modules, that have now very high responsibilities with regards of our safety. It is important to ensure that those modules will operate no matter the kind of disturbances they can be exposed to. The automotive world is a quite harsh environment for electronic systems. A major source of electrical stress is called the Electrostatic Discharge (ESD). It is a very sudden flow of electricity of large amplitude capable of destroying electronic components, or disturb them during their normal operation. This research focuses on functional failures where functionality can be temporarily lost after an ESD with various impact on the vehicle. To guarantee before manufacturing that a module and its components will perform their duty correctly, new analysis and prediction methods are required against soft-failures caused by electrostatic discharges. In this research, different approaches have been explored and proposed towards that goal. First, a modelling method for reproducing the ESD waveforms from the test generator up to the integrated circuit input is presented. It is based on a hierarchical approach where each element of the system is modelled individually, then added to the complete setup model. A practical case of functional failure at silicon-level is analyzed using simulation tools. To acquire more data on this fault, a testchip has been designed. It contains on-chip monitoring structures to measure voltage and current, and monitor function behavior directly at silicon-level. The last part of this research details different analysis methods developed for identifying efficiently functional weaknesses. The methods rely heavily on simulation tools, and prototypes have been implemented to prove the initial concepts. The first method models each function inside the chip individually, using behavioral models, then enables to connect the models together to deduce the full function's robustness. It enables hierarchical analysis of complex integrated circuit designs, to identify potential weak spots inside the circuit that could require more shielding or protection. The second method is focused on constructing equivalent electrical black box models of integrated circuit functions. The goal is to model the IC with a behavioral, black-box model capable of reproducing waveforms in powered conditions during the ESD. In summary, this research work has led to the development of several hardware and software prototypes. It has also highlighted important modelling challenges to solve in future works to achieve better functional robustness against electrostatic discharges

Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

Large military platforms have encountered major performance and reliability issues due to an increased number of incidents with counterfeit electronic parts. This has drawn the attention of Department of Defense (DOD) leadership making detection and avoidance of counterfeit electronic parts a top issue for national defense. More defined regulations and processes for identifying, reporting, and disposing of counterfeit electronic parts are being revised to raise awareness for this aggregating issue, as well as enhance the detection of these parts. Multiple technologies are currently employed throughout the supply chain to detect counterfeit electronic parts. These methods are often costly, time-consuming, and destructive. This research investigates a non-destructive test method that collects unintentionally radiated electromagnetic emissions from functional devices using a commercially available system, the APREL EM-ISight. A design of experiments (DOE) is created and exploited to determine the optimal test settings for measuring devices. The sensitivity of the system is analyzed by scanning a commercial-off-the-shelf (COTS) field-programmable gate array (FPGA) at the optimal test settings established from the DOE and varying the programmed signal. This research established the viability of using APRELs EM-ISight to detect a devices inherent electromagnetic signature. Another take away from this research is the tradeoff between resolution and scantime

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Bridges Structural Health Monitoring and Deterioration Detection Synthesis of Knowledge and Technology

INE/AUTC 10.0

Research and technology highlights of the Lewis Research Center

Highlights of research accomplishments of the Lewis Research Center for fiscal year 1984 are presented. The report is divided into four major sections covering aeronautics, space communications, space technology, and materials and structures. Six articles on energy are included in the space technology section