Channel routing for integrated optics

pre-printIncreasing scope and applications of integrated optics necessitates the development of automated techniques for physical design of optical systems. This paper presents an automated, planar channel routing technique for integrated optical waveguides. Integrated optics is a planar technology and lacks the inherent signal restoration capabilities of static-CMOS. Therefore, signal loss minimization-as a function of waveguide crossings and bends-is the primary objective of this technique. This is in contrast to track and wire-length minimization of traditional VLSI routing. Our optical channel router guarantees minimal waveguide crossings by drawing upon sorting-based techniques for waveguide routing. To further improve our solutions in terms of signal loss, we extend the router to reduce the number of bends produced during routing. Finally, we implement the optical channel routing technique and describe the experimental results, comparing the costs of routing solutions with respect to waveguide crossings, bends, and channel height

Photonics design tool for advanced CMOS nodes

Recently, the authors have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigour that is embodied in the 10 000 to 50 000 design rules that these designs must comply within advanced complementary metal-oxide semiconductor manufacturing. Here, the authors present a photonic design automation tool which allows automatic generation of layouts without design-rule violations. This tool is written in SKILL, the native language of the mainstream electric design automation software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. For the first time the authors present an algorithm for removal of design-rule violations from photonic layouts based on Manhattan discretisation, Boolean and sizing operations. This algorithm is not limited to the implementation in SKILL, and can in principle be implemented in any scripting language. Connectivity is achieved with software-defined waveguide ports and low-level procedures that enable auto-routing of waveguide connections.Comment: 5 pages, 10 figure

Characterisation of on-chip wireless interconnects based on silicon nanoantennas via near-field scanning optical microscopy

This paper is a postprint of a paper submitted to and accepted for publication in IET Optoelectronics and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.[EN] Recently, a novel Photonic-Integrated Circuit (PIC) paradigm based on the use of a new kind of ultra-directive, lowloss, highly efficient and broadband silicon nanoantenna has enabled the first demonstration of an on-chip wireless interconnect, with potential applications in reconfigurable networks and lab-on-a-chip systems. Despite the fact that the far-field properties of these nanoantennas have been widely studied, their near-field behaviour stays unexplored. Here, the authors study this feature through scanning near-field optical microscopy (SNOM). For this purpose, the authors design and characterise an on-chip twoport wireless link using a tailored SNOM. The conducted near-field measurements will be useful to improve the design of these integrated photonic devices with potential impact on a variety of applications, from biosensing to optical communications.Funding support from the Spanish Ministry of Economy and Competiveness under grants TEC2015-63838-C3-1-R OPTONANOSENS (MINECO/FEDER, UE) and TEC2015-73581-JIN PHUTURE (AEI/FEDER, UE), the EU-funded H2020-FET-HPC EXANEST (No. 671553) and the GeneralitatValenciana's PROMETEO grant NANOMET PLUS (PROMETEO II/2014/34) are acknowledged. E.P.-C. acknowledges support from GeneralitatValenciana under Grant APOSTD/2016/025.Díaz-Fernández, FJ.; Pinilla-Cienfuegos, E.; García Meca, C.; Lechago-Buendia, S.; Griol Barres, A.; Martí Sendra, J. (2019). Characterisation of on-chip wireless interconnects based on silicon nanoantennas via near-field scanning optical microscopy. IET Optoelectronics. 13(2):72-76. https://doi.org/10.1049/iet-opt.2018.5071S7276132Kirchain, R., & Kimerling, L. (2007). A roadmap for nanophotonics. Nature Photonics, 1(6), 303-305. doi:10.1038/nphoton.2007.84Zhang, Y., Watts, B., Guo, T., Zhang, Z., Xu, C., & Fang, Q. (2016). Optofluidic Device Based Microflow Cytometers for Particle/Cell Detection: A Review. Micromachines, 7(4), 70. doi:10.3390/mi7040070Redding, B., Liew, S. F., Sarma, R., & Cao, H. (2013). Compact spectrometer based on a disordered photonic chip. Nature Photonics, 7(9), 746-751. doi:10.1038/nphoton.2013.190Fan, X., & White, I. M. (2011). Optofluidic microsystems for chemical and biological analysis. Nature Photonics, 5(10), 591-597. doi:10.1038/nphoton.2011.206Condrat, C., Kalla, P., & Blair, S. (2014). Crossing-Aware Channel Routing for Integrated Optics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(6), 814-825. doi:10.1109/tcad.2014.2317575Brongersma, M. L. (2008). Engineering optical nanoantennas. Nature Photonics, 2(5), 270-272. doi:10.1038/nphoton.2008.60Bellanca, G., Calò, G., Kaplan, A. E., Bassi, P., & Petruzzelli, V. (2017). Integrated Vivaldi plasmonic antenna for wireless on-chip optical communications. Optics Express, 25(14), 16214. doi:10.1364/oe.25.016214Krasnok, A. E., Miroshnichenko, A. E., Belov, P. A., & Kivshar, Y. S. (2012). All-dielectric optical nanoantennas. Optics Express, 20(18), 20599. doi:10.1364/oe.20.020599Krasnok, A. E., Simovski, C. R., Belov, P. A., & Kivshar, Y. S. (2014). Superdirective dielectric nanoantennas. Nanoscale, 6(13), 7354-7361. doi:10.1039/c4nr01231cGarcía-Meca, C., Lechago, S., Brimont, A., Griol, A., Mas, S., Sánchez, L., … Martí, J. (2017). On-chip wireless silicon photonics: from reconfigurable interconnects to lab-on-chip devices. Light: Science & Applications, 6(9), e17053-e17053. doi:10.1038/lsa.2017.53Kosako, T., Kadoya, Y., & Hofmann, H. F. (2010). Directional control of light by a nano-optical Yagi–Uda antenna. Nature Photonics, 4(5), 312-315. doi:10.1038/nphoton.2010.34Dvořák, P., Édes, Z., Kvapil, M., Šamořil, T., Ligmajer, F., Hrtoň, M., … Šikola, T. (2017). Imaging of near-field interference patterns by aperture-type SNOM – influence of illumination wavelength and polarization state. Optics Express, 25(14), 16560. doi:10.1364/oe.25.016560Bazylewski, P., Ezugwu, S., & Fanchini, G. (2017). A Review of Three-Dimensional Scanning Near-Field Optical Microscopy (3D-SNOM) and Its Applications in Nanoscale Light Management. Applied Sciences, 7(10), 973. doi:10.3390/app710097

Crossing-aware channel routing for photonic waveguides

pre-printAbstract-Silicon photonics technology is progressing at a rapid pace. Despite greatly expanded manufacturing capability, physical design of integrated optical circuits currently lacks the level of automation found in VLSI design. A key component of integrated optic design is waveguide routing; however, unlike VLSI, where signal nets are routed with metal layers and vias, photonic waveguides are fabricated in planar substrates. For many applications, our studies show that the waveguide routing problem can be formulated as planar channel routing. Signal losses become a major factor due to the insertion losses of planar waveguide crossings. Channel routing must therefore take into account these losses. This paper investigates methods for adapting traditional VLSI channel routing techniques for integrated optics - specifically, a technique based on left-edge-style track assignment. We show how incorporating waveguide crossing constraints into the underlying constraint model affects the routing solution, and describe the necessary modifications and extensions to the routing technique to properly exploit optical technology. We implement the channel router, describe the experimental results, and compare the cost of solutions with respect to waveguide crossings, corresponding to signal loss, and channel height

Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics

On-chip wireless silicon photonics: From reconfigurable interconnects to lab-on-chip devices

[EN] Photonic integrated circuits are developing as key enabling components for high-performance computing and advanced network-on-chip, as well as other emerging technologies such as lab-on-chip sensors, with relevant applications in areas from medicine and biotechnology to aerospace. These demanding applications will require novel features, such as dynamically reconfigurable light pathways, obtained by properly harnessing on-chip optical radiation. In this paper, we introduce a broadband, high-directivity (>150), low-loss, and reconfigurable silicon photonics nanoantenna that fully enables on-chip radiation control. We propose the use of these nanoantennas as versatile building blocks to develop wireless (unguided) silicon photonic devices, which considerably enhance the range of achievable integrated photonic functionalities. As examples of applications, we demonstrate 160 Gbit·s-1 data transmission over mm-scale wireless interconnects, a compact low-crosstalk 12-port crossing, and electrically reconfigurable pathways via optical beam steering. Moreover, the realization of a flow micro-cytometer for particle characterization demonstrates the smart system integration potential of our approach as lab-on-chip devices.Funding from grant TEC2015-63838-C3-1-R OPTONANOSENS (MINECO/FEDER, UE) is acknowledged. This work was also supported by project TEC2015-73581-JIN (AEI/FEDER, UE), the EU-funded projects FP7-ICT PHOXTROT (No.318240) and H2020-, the EU-funded H2020-FET-HPC EXANEST (No.671553) and the Generalitat Valenciana's PROMETEO grant NANOMET PLUS (PROMETEO II/2014/34) CG-M acknowledges support from Generalitat Valenciana’s VALi+d postdoctoral program (exp. APOSTD/ 2014/044). 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Multimode interference devices for focusing in microfluidic channels. Opt Lett 2011; 36: 3067–3069

Master of Science

thesisAdvances in silicon photonics are enabling hybrid integration of optoelectronic circuits alongside current complementary metal-oxide-semiconductor (CMOS) technologies. To fully exploit the capability of this integration, it is important to explore the effects of thermal gradients on optoelectronic devices. The sensitivity of optical components to temperature variation gives rise to design issues in silicon on insulator (SOI) optoelectronic technology. The thermo-electric effect becomes problematic with the integration of hybrid optoelectronic systems, where heat is generated from electrical components. Through the thermo-optic effect, the optical signals are in turn affected and compensation is necessary. To improve the capability of optical SOI designs, optical-wave-simulation models and the characteristic thermal operating environment need to be integrated to ensure proper operation. In order to exploit the potential for compensation by virtue of resynthesis, temperature characterization on a system level is required. Thermal characterization within the flow of physical design automation tools for hybrid optoelectronic technology enables device resynthesis and validation at a system level. Additionally, thermally-aware routing and placement would be possible. A simplified abstraction will help in the active design process, within the contemporary computer-aided design (CAD) flow when designing optoelectronic features. This thesis investigates an abstraction model to characterize the effect of a temperature gradient on optoelectronic circuit operation. To make the approach scalable, reduced order computations are desired that effectively model the effect of temperature on an optoelectronic layout; this is achieved using an electrical analogy to heat flow. Given an optoelectronic circuit, using a thermal resistance network to abstract thermal flow, we compute the temperature distribution throughout the layout. Subsequently, we show how this thermal distribution across the optoelectronic system layout can be integrated within optoelectronic device- and system-level analysis tools

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects