21 research outputs found
Channel Characterization for Chip-scale Wireless Communications within Computing Packages
Wireless Network-on-Chip (WNoC) appears as a promising alternative to
conventional interconnect fabrics for chip-scale communications. WNoC takes
advantage of an overlaid network composed by a set of millimeter-wave antennas
to reduce latency and increase throughput in the communication between cores.
Similarly, wireless inter-chip communication has been also proposed to improve
the information transfer between processors, memory, and accelerators in
multi-chip settings. However, the wireless channel remains largely unknown in
both scenarios, especially in the presence of realistic chip packages. This
work addresses the issue by accurately modeling flip-chip packages and
investigating the propagation both its interior and its surroundings. Through
parametric studies, package configurations that minimize path loss are obtained
and the trade-offs observed when applying such optimizations are discussed.
Single-chip and multi-chip architectures are compared in terms of the path loss
exponent, confirming that the amount of bulk silicon found in the pathway
between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on
Networks-on-Chip (NOCS 2018); Torino, Italy; October 201
Collective Communication Patterns Using Time-Reversal Terahertz Links at the Chip Scale
Wireless communications in the terahertz band have been recently proposed as
complement to conventional wired interconnects within computing packages. Such
environments are typically highly reverberant, hence showing long channel
impulse responses and severely limiting the achievable rates. Fortunately, this
communications scenario is static and can be pre-characterized, which opens the
door to techniques such as time reversal. Time reversal acts a spatial matched
filter and has a spatiotemporal focusing effect, which allows not only to
increase the achievable symbol rates, but also to create multiple spatial
channels. In this paper, the multi-user capability of time reversal is explored
in the context of wireless communications in the terahertz band within a
computing package. Full-wave simulations are carried out to validate the
approach, whereas modulation streams are simulated to evaluate the error rate
as a function of the transmitted power, symbol rate, and number of simultaneous
transmissions
Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case
Network-on-Chip (NoC) is currently the paradigm of choice to interconnect the
different components of System-on-Chips (SoCs) or Chip Multiprocessors (CMPs).
As the levels of integration continue to grow, however, current NoCs face
significant scalability limitations and have prompted research in novel
interconnect technologies. Among these, wireless intra-chip communications have
been under intense scrutiny due to their low latency broadcast and
architectural flexibility. Thus far, the practicality of the idea has been
studied from the RF front-end and the network interface perspectives, whereas
little to no attention has been placed on another essential component: the data
converters. This article aims to fill this gap by providing a comprehensive
analysis of the requirements of the scenario, as well as of the current
performance and cost trends of Analog-to-Digital Converters (ADCs). Based on
Murmann's data, we demonstrate that ADCs will not be a roadblock for the
realization of wireless intra-chip communications although current designs do
not meet their demands fully.Comment: Presented at DCIS 201
Channel characterization for chip-scale wireless communications within computing packages
Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Peer ReviewedPostprint (author's final draft
On the nanocommunications at THz band in graphene-enabled wireless network-on-chip
One of the main challenges towards the growing computation-intensive applications with scalable bandwidth requirement is the deployment of a dense number of on-chip cores within a chip package. To this end, this paper investigates the Wireless Network-on-Chip (WiNoC), which is enabled by graphene- based nanoantennas (GNAs) in Terahertz frequency band. We first develop a channel model between the GNAs taking into account the practical issues of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the GNAs. In the Terahertz band, not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) caused by various molecules and their isotopologues within the chip package constitute the loss of signal transmission. We further propose an optimal power allocation to achieve the channel capacity subject to transmit power constraint. By analysing the effects of the MAA on the path loss and channel capacity, the proposed channel model shows that the MAA significantly degrades the performance at certain frequency ranges, e.g. 1.21 THz, 1.28 THz and 1.45 THz, of up to 31.8% compared to the conventional channel model, even when the GNAs are very closely located of only 0.01 mm. More specifically, at transmission frequency of 1 THz, the channel capacity of the proposed model is shown to be much lower than that of the conventional model over the whole range of temperature and ambient pressure of up to 26.8% and 25%, respectively. Finally, simulation results are provided to verify the analytical findings
Multi-level analysis of on-chip optical wireless links
Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of \u3bcm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip
Multi-level analysis of on-chip optical wireless links
Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of ÎĽm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip
Computing and communications for the software-defined metamaterial paradigm: a context analysis
Metamaterials are artificial structures that have recently enabled the realization of novel electromagnetic components with engineered and even unnatural functionalities. Existing metamaterials are specifically designed for a single application working under preset conditions (e.g., electromagnetic cloaking for a fixed angle of incidence) and cannot be reused. Software-defined metamaterials (SDMs) are a much sought-after paradigm shift, exhibiting electromagnetic properties that can be reconfigured at runtime using a set of software primitives. To enable this new technology, SDMs require the integration of a network of controllers within the structure of the metamaterial, where each controller interacts locally and communicates globally to obtain the programmed behavior. The design approach for such controllers and the interconnection network, however, remains unclear due to the unique combination of constraints and requirements of the scenario. To bridge this gap, this paper aims to provide a context analysis from the computation and communication perspectives. Then, analogies are drawn between the SDM scenario and other applications both at the micro and nano scales, identifying possible candidates for the implementation of the controllers and the intra-SDM network. Finally, the main challenges of SDMs related to computing and communications are outlined.Peer ReviewedPostprint (published version