On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

page number: 12International audienceWith the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins

Otimização e melhoria da modulação comportamental para os interfaces de E/S analógica e de sinal misto de alta velocidade

Doutoramento em Engenharia ElectrotécnicaA integridade do sinal em sistemas digitais interligados de alta velocidade, e avaliada através da simulação de modelos físicos (de nível de transístor) é custosa de ponto vista computacional (por exemplo, em tempo de execução de CPU e armazenamento de memória), e exige a disponibilização de detalhes físicos da estrutura interna do dispositivo. Esse cenário aumenta o interesse pela alternativa de modelação comportamental que descreve as características de operação do equipamento a partir da observação dos sinais eléctrico de entrada/saída (E/S). Os interfaces de E/S em chips de memória, que mais contribuem em carga computacional, desempenham funções complexas e incluem, por isso, um elevado número de pinos. Particularmente, os buffers de saída são obrigados a distorcer os sinais devido à sua dinâmica e não linearidade. Portanto, constituem o ponto crítico nos de circuitos integrados (CI) para a garantia da transmissão confiável em comunicações digitais de alta velocidade. Neste trabalho de doutoramento, os efeitos dinâmicos não-lineares anteriormente negligenciados do buffer de saída são estudados e modulados de forma eficiente para reduzir a complexidade da modelação do tipo caixa-negra paramétrica, melhorando assim o modelo standard IBIS. Isto é conseguido seguindo a abordagem semi-física que combina as características de formulação do modelo caixa-negra, a análise dos sinais eléctricos observados na E/S e propriedades na estrutura física do buffer em condições de operação práticas. Esta abordagem leva a um processo de construção do modelo comportamental fisicamente inspirado que supera os problemas das abordagens anteriores, optimizando os recursos utilizados em diferentes etapas de geração do modelo (ou seja, caracterização, formulação, extracção e implementação) para simular o comportamento dinâmico não-linear do buffer. Em consequência, contributo mais significativo desta tese é o desenvolvimento de um novo modelo comportamental analógico de duas portas adequado à simulação em overclocking que reveste de um particular interesse nas mais recentes usos de interfaces de E/S para memória de elevadas taxas de transmissão. A eficácia e a precisão dos modelos comportamentais desenvolvidos e implementados são qualitativa e quantitativamente avaliados comparando os resultados numéricos de extracção das suas funções e de simulação transitória com o correspondente modelo de referência do estado-da-arte, IBIS.Signal integrity (SI) simulation of high-speed digital interconnected system via transistor level models is computational expensive (e.g. CPU time and memory storage), and requires the availability of physical details information of device’s internal structure. This scenario raises the interest for a behavioral modeling alternative which describes the device’s operation characteristics based on the observed input/output (I/O) electrical signal. I/O buffers that interface memory’s interconnects have major share in the computational load containing a very active complex functional part and high numbers of pins. Particularly, output buffers/drivers are forced to distort the I/O signals due to their nonlinear dynamics. In this concern, they constitute the integrated circuit (IC) bottleneck of ensuring reliable data transmission in the high-speed digital communication link. In this PhD work, the previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation, the analysis of the observed I/O electrical signals and the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. Moreover, the most important achievement is the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities

Closed-form crosstalk noise metrics for physical design applications

ABSTRACT In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced crosstalk noise for distributed RC coupling trees. The efficiency of our approach stems from the fact that only the five basic operations are used in the expressions: addition ( ), subtraction ( ), multiplication ( ), division ( ) and square root ( ). The formulas do not require exponent computation or numerical iterations. We have developed closed-form expressions for the peak crosstalk noise amplitude, the peak noise occurring time and the width of the noise waveform. Our approximations are conservative and yet achieve acceptable accuracy. The formulas are simple enough to be used in the inner loops of performance optimization algorithms or as cost functions to guide routers. They capture the influence of coupling direction (near-end and far-end coupling) and coupling location (near-driver and nearreceiver)

Computational Electrodynamics and Simulation in High Speed Circuit Using Finite Difference Time Domain (FDTD) Method

High speed signaling over a significant length is an important issue for high speed electronic devices such as Ethernet network routers. With increasing demands on high-quality and fast communication, circuit design for high speed signaling becomes more important than ever. As frequency increases, signal integrity may decrease to a point where the system or device fails. Accurate simulation of electromagnetic wave propagating in the circuits becomes critical in today’s design cycle for high speed devices. This thesis work developed a simulation tool for characterizing high speed circuit, using Finite Difference Time Domain (FDTD) method. The FDTD calculates the 3-D electromagnetic propagation numerically in the structure of a printed circuit board (PCB). It provides S-parameters, and wave propagation monitoring to assist engineers for analyzing signal integrity of a PCB for high speed circuits. The simulation tool is working properly and matches the result form other software and measurement tool, such as CST. This thesis introduces signal integrity, numerical method for simulating electromagnetic propagation, design and development a FDTD tool for circuit simulations, and validation results of the tool

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Sincronização em sistemas integrados a alta velocidade

Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm

Multiple Track Performance of a Digital Magnetic Tape System : Experimental Study and Simulation using Parallel Processing Techniques

The primary aim of the magnetic recording industry is to increase storage capacities and transfer rates whilst maintaining or reducing costs. In multiple-track tape systems, as recorded track dimensions decrease, higher precision tape transport mechanisms and dedicated coding circuitry are required. This leads to increased manufacturing costs and a loss of flexibility. This thesis reports on the performance of a low precision low-cost multiple-track tape transport system. Software based techniques to study system performance, and to compensate for the mechanical deficiencies of this system were developed using occam and the transputer. The inherent parallelism of the multiple-track format was exploited by integrating a transputer into the recording channel to perform the signal processing tasks. An innovative model of the recording channel, written exclusively in occam, was developed. The effect of parameters, such as data rate, track dimensions and head misregistration on system performance was determined from the detailed error profile produced. This model may be run on a network of transputers, allowing its speed of execution to be scaled to suit the investigation. These features, combined with its modular flexibility makes it a powerful tool that may be applied to other multiple-track systems, such as digital HDTV. A greater understanding of the effects of mechanical deficiencies on the performance of multiple-track systems was gained from this study. This led to the development of a software based compensation scheme to reduce the effects of Lateral Head Displacement and allow low-cost tape transport mechanisms to be used with narrow, closely spaced tracks, facilitating higher packing densities. The experimental and simulated investigation of system performance, the development of the model and compensation scheme using parallel processing techniques has led to the publication of a paper and two further publications are expected.Thorn EMI, Central Research Laboratories, Hayes, Middlese

Micro Fourier Transform Profilometry (μ\muFTP): 3D shape measurement at 10,000 frames per second

Recent advances in imaging sensors and digital light projection technology have facilitated a rapid progress in 3D optical sensing, enabling 3D surfaces of complex-shaped objects to be captured with improved resolution and accuracy. However, due to the large number of projection patterns required for phase recovery and disambiguation, the maximum fame rates of current 3D shape measurement techniques are still limited to the range of hundreds of frames per second (fps). Here, we demonstrate a new 3D dynamic imaging technique, Micro Fourier Transform Profilometry ($\mu$FTP), which can capture 3D surfaces of transient events at up to 10,000 fps based on our newly developed high-speed fringe projection system. Compared with existing techniques, $\mu$FTP has the prominent advantage of recovering an accurate, unambiguous, and dense 3D point cloud with only two projected patterns. Furthermore, the phase information is encoded within a single high-frequency fringe image, thereby allowing motion-artifact-free reconstruction of transient events with temporal resolution of 50 microseconds. To show $\mu$FTP's broad utility, we use it to reconstruct 3D videos of 4 transient scenes: vibrating cantilevers, rotating fan blades, bullet fired from a toy gun, and balloon's explosion triggered by a flying dart, which were previously difficult or even unable to be captured with conventional approaches.Comment: This manuscript was originally submitted on 30th January 1