55 research outputs found
Energy-Aware Data Movement In Non-Volatile Memory Hierarchies
While technology scaling enables increased density for memory cells, the intrinsic high leakage power of conventional CMOS technology and the demand for reduced energy consumption inspires the use of emerging technology alternatives such as eDRAM and Non-Volatile Memory (NVM) including STT-MRAM, PCM, and RRAM. The utilization of emerging technology in Last Level Cache (LLC) designs which occupies a signifcant fraction of total die area in Chip Multi Processors (CMPs) introduces new dimensions of vulnerability, energy consumption, and performance delivery. To be specific, a part of this research focuses on eDRAM Bit Upset Vulnerability Factor (BUVF) to assess vulnerable portion of the eDRAM refresh cycle where the critical charge varies depending on the write voltage, storage and bit-line capacitance. This dissertation broaden the study on vulnerability assessment of LLC through investigating the impact of Process Variations (PV) on narrow resistive sensing margins in high-density NVM arrays, including on-chip cache and primary memory. Large-latency and power-hungry Sense Amplifers (SAs) have been adapted to combat PV in the past. Herein, a novel approach is proposed to leverage the PV in NVM arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time. On the other hand, this dissertation investigates a novel technique to prioritize the service to 1) Extensive Read Reused Accessed blocks of the LLC that are silently dropped from higher levels of cache, and 2) the portion of the working set that may exhibit distant re-reference interval in L2. In particular, we develop a lightweight Multi-level Access History Profiler to effciently identify ERRA blocks through aggregating the LLC block addresses tagged with identical Most Signifcant Bits into a single entry. Experimental results indicate that the proposed technique can reduce the L2 read miss ratio by 51.7% on average across PARSEC and SPEC2006 workloads. In addition, this dissertation will broaden and apply advancements in theories of subspace recovery to pioneer computationally-aware in-situ operand reconstruction via the novel Logic In Interconnect (LI2) scheme. LI2 will be developed, validated, and re?ned both theoretically and experimentally to realize a radically different approach to post-Moore\u27s Law computing by leveraging low-rank matrices features offering data reconstruction instead of fetching data from main memory to reduce energy/latency cost per data movement. We propose LI2 enhancement to attain high performance delivery in the post-Moore\u27s Law era through equipping the contemporary micro-architecture design with a customized memory controller which orchestrates the memory request for fetching low-rank matrices to customized Fine Grain Reconfigurable Accelerator (FGRA) for reconstruction while the other memory requests are serviced as before. The goal of LI2 is to conquer the high latency/energy required to traverse main memory arrays in the case of LLC miss, by using in-situ construction of the requested data dealing with low-rank matrices. Thus, LI2 exchanges a high volume of data transfers with a novel lightweight reconstruction method under specific conditions using a cross-layer hardware/algorithm approach
Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy
[Abstract] On-chip power consumption is one of the fundamental challenges of current technology scaling. Cache memories consume a sizable part of this power, particularly due to leakage energy. STT-RAM is one of several new memory technologies that have been proposed in order to improve power while preserving performance. It features high density and low leakage, but at the expense of write energy and performance. This article explores the use of STT-RAM--based scratchpad memories that trade nonvolatility in exchange for faster and less energetically expensive accesses, making them feasible for on-chip implementation in embedded systems. A novel multiretention scratchpad partitioning is proposed, featuring multiple storage spaces with different retention, energy, and performance characteristics. A customized compiler-based allocation algorithm suitable for use with such a scratchpad organization is described. Our experiments indicate that a multiretention STT-RAM scratchpad can provide energy savings of 53% with respect to an iso-area, hardware-managed SRAM cache
새로운 메모리 기술을 기반으로 한 메모리 시스템 설계 기술
학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 최기영.Performance and energy efficiency of modern computer systems are largely dominated by the memory system. This memory bottleneck has been exacerbated in the past few years with (1) architectural innovations for improving the efficiency of computation units (e.g., chip multiprocessors), which shift the major cause of inefficiency from processors to memory, and (2) the emergence of data-intensive applications, which demands a large capacity of main memory and an excessive amount of memory bandwidth to efficiently handle such workloads. In order to address this memory wall challenge, this dissertation aims at exploring the potential of emerging memory technologies and designing a high-performance, energy-efficient memory hierarchy that is aware of and leverages the characteristics of such new memory technologies.
The first part of this dissertation focuses on energy-efficient on-chip cache design based on a new non-volatile memory technology called Spin-Transfer Torque RAM (STT-RAM). When STT-RAM is used to build on-chip caches, it provides several advantages over conventional charge-based memory (e.g., SRAM or eDRAM), such as non-volatility, lower static power, and higher density. However, simply replacing SRAM caches with STT-RAM rather increases the energy consumption because write operations of STT-RAM are slower and more energy-consuming than those of SRAM.
To address this challenge, we propose four novel architectural techniques that can alleviate the impact of inefficient STT-RAM write operations on system performance and energy consumption. First, we apply STT-RAM to instruction caches (where write operations are relatively infrequent) and devise a power-gating mechanism called LASIC, which leverages the non-volatility of STT-RAM to turn off STT-RAM instruction caches inside small loops. Second, we propose lower-bits cache, which exploits the narrow bit-width characteristics of application data by caching frequent bit-flips at lower bits in a small SRAM cache. Third, we present prediction hybrid cache, an SRAM/STT-RAM hybrid cache whose block placement between SRAM and STT-RAM is determined by predicting the write intensity of each cache block with a new hardware structure called write intensity predictor. Fourth, we propose DASCA, which predicts write operations that can bypass the cache without incurring extra cache misses (called dead writes) and lets the last-level cache bypass such dead writes to reduce write energy consumption.
The second part of this dissertation architects intelligent main memory and its host architecture support based on logic-enabled DRAM. Traditionally, main memory has served the sole purpose of storing data because the extra manufacturing cost of implementing rich functionality (e.g., computation) on a DRAM die was unacceptably high. However, the advent of 3D die stacking now provides a practical, cost-effective way to integrate complex logic circuits into main memory, thereby opening up the possibilities for intelligent main memory. For example, it can be utilized to implement advanced memory management features (e.g., scheduling, power management, etc.) inside memoryit can be also used to offload computation to main memory, which allows us to overcome the memory bandwidth bottleneck caused by narrow off-chip channels (commonly known as processing-in-memory or PIM). The remaining questions are what to implement inside main memory and how to integrate and expose such new features to existing systems.
In order to answer these questions, we propose four system designs that utilize logic-enabled DRAM to improve system performance and energy efficiency. First, we utilize the existing logic layer of a Hybrid Memory Cube (a commercial logic-enabled DRAM product) to (1) dynamically turn off some of its off-chip links by monitoring the actual bandwidth demand and (2) integrate prefetch buffer into main memory to perform aggressive prefetching without consuming off-chip link bandwidth. Second, we propose a scalable accelerator for large-scale graph processing called Tesseract, in which graph processing computation is offloaded to specialized processors inside main memory in order to achieve memory-capacity-proportional performance. Third, we design a low-overhead PIM architecture for near-term adoption called PIM-enabled instructions, where PIM operations are interfaced as cache-coherent, virtually-addressed host processor instructions that can be executed either by the host processor or in main memory depending on the data locality. Fourth, we propose an energy-efficient PIM system called aggregation-in-memory, which can adaptively execute PIM operations at any level of the memory hierarchy and provides a fully automated compiler toolchain that transforms existing applications to use PIM operations without programmer intervention.Chapter 1 Introduction 1
1.1 Inefficiencies in the Current Memory Systems 2
1.1.1 On-Chip Caches 2
1.1.2 Main Memory 2
1.2 New Memory Technologies: Opportunities and Challenges 3
1.2.1 Energy-Efficient On-Chip Caches based on STT-RAM 3
1.2.2 Intelligent Main Memory based on Logic-Enabled DRAM 6
1.3 Dissertation Overview 9
Chapter 2 Previous Work 11
2.1 Energy-Efficient On-Chip Caches based on STT-RAM 11
2.1.1 Hybrid Caches 11
2.1.2 Volatile STT-RAM 13
2.1.3 Redundant Write Elimination 14
2.2 Intelligent Main Memory based on Logic-Enabled DRAM 15
2.2.1 PIM Architectures in the 1990s 15
2.2.2 Modern PIM Architectures based on 3D Stacking 15
2.2.3 Modern PIM Architectures on Memory Dies 17
Chapter 3 Loop-Aware Sleepy Instruction Cache 19
3.1 Architecture 20
3.1.1 Loop Cache 21
3.1.2 Loop-Aware Sleep Controller 22
3.2 Evaluation and Discussion 24
3.2.1 Simulation Environment 24
3.2.2 Energy 25
3.2.3 Performance 27
3.2.4 Sensitivity Analysis 27
3.3 Summary 28
Chapter 4 Lower-Bits Cache 29
4.1 Architecture 29
4.2 Experiments 32
4.2.1 Simulator and Cache Model 32
4.2.2 Results 33
4.3 Summary 34
Chapter 5 Prediction Hybrid Cache 35
5.1 Problem and Motivation 37
5.1.1 Problem Definition 37
5.1.2 Motivation 37
5.2 Write Intensity Predictor 38
5.2.1 Keeping Track of Trigger Instructions 39
5.2.2 Identifying Hot Trigger Instructions 40
5.2.3 Dynamic Set Sampling 41
5.2.4 Summary 42
5.3 Prediction Hybrid Cache 43
5.3.1 Need for Write Intensity Prediction 43
5.3.2 Organization 43
5.3.3 Operations 44
5.3.4 Dynamic Threshold Adjustment 45
5.4 Evaluation Methodology 48
5.4.1 Simulator Configuration 48
5.4.2 Workloads 50
5.5 Single-Core Evaluations 51
5.5.1 Energy Consumption and Speedup 51
5.5.2 Energy Breakdown 53
5.5.3 Coverage and Accuracy 54
5.5.4 Sensitivity to Write Intensity Threshold 55
5.5.5 Impact of Dynamic Set Sampling 55
5.5.6 Results for Non-Write-Intensive Workloads 56
5.6 Multicore Evaluations 57
5.7 Summary 59
Chapter 6 Dead Write Prediction Assisted STT-RAM Cache 61
6.1 Motivation 62
6.1.1 Energy Impact of Inefficient Write Operations 62
6.1.2 Limitations of Existing Approaches 63
6.1.3 Potential of Dead Writes 64
6.2 Dead Write Classification 65
6.2.1 Dead-on-Arrival Fills 65
6.2.2 Dead-Value Fills 66
6.2.3 Closing Writes 66
6.2.4 Decomposition 67
6.3 Dead Write Prediction Assisted STT-RAM Cache Architecture 68
6.3.1 Dead Write Prediction 68
6.3.2 Bidirectional Bypass 71
6.4 Evaluation Methodology 72
6.4.1 Simulation Configuration 72
6.4.2 Workloads 74
6.5 Evaluation for Single-Core Systems 75
6.5.1 Energy Consumption and Speedup 75
6.5.2 Coverage and Accuracy 78
6.5.3 Sensitivity to Signature 78
6.5.4 Sensitivity to Update Policy 80
6.5.5 Implications of Device-/Circuit-Level Techniques for Write Energy Reduction 80
6.5.6 Impact of Prefetching 80
6.6 Evaluation for Multi-Core Systems 81
6.6.1 Energy Consumption and Speedup 81
6.6.2 Application to Inclusive Caches 83
6.6.3 Application to Three-Level Cache Hierarchy 84
6.7 Summary 85
Chapter 7 Link Power Management for Hybrid Memory Cubes 87
7.1 Background and Motivation 88
7.1.1 Hybrid Memory Cube 88
7.1.2 Motivation 89
7.2 HMC Link Power Management 91
7.2.1 Link Delay Monitor 91
7.2.2 Power State Transition 94
7.2.3 Overhead 95
7.3 Two-Level Prefetching 95
7.4 Application to Multi-HMC Systems 97
7.5 Experiments 98
7.5.1 Methodology 98
7.5.2 Link Energy Consumption and Speedup 100
7.5.3 HMC Energy Consumption 102
7.5.4 Runtime Behavior of LPM 102
7.5.5 Sensitivity to Slowdown Threshold 104
7.5.6 LPM without Prefetching 104
7.5.7 Impact of Prefetching on Link Traffic 105
7.5.8 On-Chip Prefetcher Aggressiveness in 2LP 107
7.5.9 Tighter Off-Chip Bandwidth Margin 107
7.5.10 Multithreaded Workloads 108
7.5.11 Multi-HMC Systems 109
7.6 Summary 111
Chapter 8 Tesseract PIM System for Parallel Graph Processing 113
8.1 Background and Motivation 115
8.1.1 Large-Scale Graph Processing 115
8.1.2 Graph Processing on Conventional Systems 117
8.1.3 Processing-in-Memory 118
8.2 Tesseract Architecture 119
8.2.1 Overview 119
8.2.2 Remote Function Call via Message Passing 122
8.2.3 Prefetching 124
8.2.4 Programming Interface 126
8.2.5 Application Mapping 127
8.3 Evaluation Methodology 128
8.3.1 Simulation Configuration 128
8.3.2 Workloads 129
8.4 Evaluation Results 130
8.4.1 Performance 130
8.4.2 Iso-Bandwidth Comparison 133
8.4.3 Execution Time Breakdown 134
8.4.4 Prefetch Efficiency 134
8.4.5 Scalability 135
8.4.6 Effect of Higher Off-Chip Network Bandwidth 136
8.4.7 Effect of Better Graph Distribution 137
8.4.8 Energy/Power Consumption and Thermal Analysis 138
8.5 Summary 139
Chapter 9 PIM-Enabled Instructions 141
9.1 Potential of ISA Extensions as the PIM Interface 143
9.2 PIM Abstraction 145
9.2.1 Operations 145
9.2.2 Memory Model 147
9.2.3 Software Modification 148
9.3 Architecture 148
9.3.1 Overview 148
9.3.2 PEI Computation Unit (PCU) 149
9.3.3 PEI Management Unit (PMU) 150
9.3.4 Virtual Memory Support 153
9.3.5 PEI Execution 153
9.3.6 Comparison with Active Memory Operations 154
9.4 Target Applications for Case Study 155
9.4.1 Large-Scale Graph Processing 155
9.4.2 In-Memory Data Analytics 156
9.4.3 Machine Learning and Data Mining 157
9.4.4 Operation Summary 157
9.5 Evaluation Methodology 158
9.5.1 Simulation Configuration 158
9.5.2 Workloads 159
9.6 Evaluation Results 159
9.6.1 Performance 160
9.6.2 Sensitivity to Input Size 163
9.6.3 Multiprogrammed Workloads 164
9.6.4 Balanced Dispatch: Idea and Evaluation 165
9.6.5 Design Space Exploration for PCUs 165
9.6.6 Performance Overhead of the PMU 167
9.6.7 Energy, Area, and Thermal Issues 167
9.7 Summary 168
Chapter 10 Aggregation-in-Memory 171
10.1 Motivation 173
10.1.1 Rethinking PIM for Energy Efficiency 173
10.1.2 Aggregation as PIM Operations 174
10.2 Architecture 176
10.2.1 Overview 176
10.2.2 Programming Model 177
10.2.3 On-Chip Caches 177
10.2.4 Coherence and Consistency 181
10.2.5 Main Memory 181
10.2.6 Potential Generalization Opportunities 183
10.3 Compiler Support 184
10.4 Contributions over Prior Art 185
10.4.1 PIM-Enabled Instructions 185
10.4.2 Parallel Reduction in Caches 187
10.4.3 Row Buffer Locality of DRAM Writes 188
10.5 Target Applications 188
10.6 Evaluation Methodology 190
10.6.1 Simulation Configuration 190
10.6.2 Hardware Overhead 191
10.6.3 Workloads 192
10.7 Evaluation Results 192
10.7.1 Energy Consumption and Performance 192
10.7.2 Dynamic Energy Breakdown 196
10.7.3 Comparison with Aggressive Writeback 197
10.7.4 Multiprogrammed Workloads 198
10.7.5 Comparison with Intrinsic-based Code 198
10.8 Summary 199
Chapter 11 Conclusion 201
11.1 Energy-Efficient On-Chip Caches based on STT-RAM 202
11.2 Intelligent Main Memory based on Logic-Enabled DRAM 203
Bibliography 205
요약 227Docto
Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency
Persistent memory provides high-performance data persistence at main memory.
Memory writes need to be performed in strict order to satisfy storage
consistency requirements and enable correct recovery from system crashes.
Unfortunately, adhering to such a strict order significantly degrades system
performance and persistent memory endurance. This paper introduces a new
mechanism, Loose-Ordering Consistency (LOC), that satisfies the ordering
requirements at significantly lower performance and endurance loss. LOC
consists of two key techniques. First, Eager Commit eliminates the need to
perform a persistent commit record write within a transaction. We do so by
ensuring that we can determine the status of all committed transactions during
recovery by storing necessary metadata information statically with blocks of
data written to memory. Second, Speculative Persistence relaxes the write
ordering between transactions by allowing writes to be speculatively written to
persistent memory. A speculative write is made visible to software only after
its associated transaction commits. To enable this, our mechanism supports the
tracking of committed transaction ID and multi-versioning in the CPU cache. Our
evaluations show that LOC reduces the average performance overhead of memory
persistence from 66.9% to 34.9% and the memory write traffic overhead from
17.1% to 3.4% on a variety of workloads.Comment: This paper has been accepted by IEEE Transactions on Parallel and
Distributed System
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