New virtually scaling free adaptive CORDIC rotator

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2

CORDIC algorithm and its applications

openThe CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation.The CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation

Real-Time RF-DNA Fingerprinting of ZigBee Devices Using a Software-Defined Radio with FPGA Processing

ZigBee networks are increasingly popular for use in medical, industrial, and other applications. Traditional security techniques for ZigBee networks are based on presenting and verifying device bit-level credentials (e.g. keys). While historically effective, ZigBee networks remain vulnerable to attack by any unauthorized rogue device that can obtain and present bit-level credentials for an authorized device. This research focused on utilizing a National Instruments (NI) X310 Software-Defined Radio (SDR) hosting an on-board Field Programmable Gate Array (FPGA). The demonstrations included device discrimination assessments using like-model ZigBee AVR RZUSBstick devices and included generating RF fingerprints in real-time, as an extension to AFIT\u27s RF-DNA fingerprinting work. The goal was to develop a fingerprinting process that was both 1) effective at discriminating between like-model ZigBee devices and 2) efficient for implementation in FPGA hardware. As designed and implemented, the full-dimensional FPGA fingerprint generator only utilized approximately 7% of the X310 Kintex-7 FPGA resources. The full-dimensional fingerprinting performance of using only 7% of FPGA resources demonstrates the feasibility for real-time RF-DNA fingerprint generation and like-model ZigBee device discrimination using an SDR platform

Study of CORDIC based processing element for digital signal processing algorithms

There is a high demand for the efficient implementation of complex arithmetic operations in many Digital Signal Processing (DSP) algorithms. The COordinate Rotation DIgital Computer (CORDIC) algorithm is suitable to be implemented in DSP algorithms since its calculation for complex arithmetic is simple and elegant. Besides, since it avoids using multiplications, adopting the CORDIC algorithm can reduce the complexity. Here, in this project CORDIC based processing element for the construction of digital signal processing algorithms is implemented. This is a flexible device that can be used in the implementation of functions such as Singular Value Decomposition (SVD), Discrete Cosine Transform (DCT) as well as many other important functions. It uses a CORDIC module to perform arithmetic operations and the result is a flexible computational processing element (PE) for digital signal processing algorithms. To implement the CORDIC based architectures for functions like SVD and DCT, it is required to decompose their computations in terms of CORDIC operations. SVD is widely used in digital signal processing applications such as direction estimation, recursive least squares (RLS) filtering and system identification. Two different Jacobi-type methods for SVD parallel computation are usually considered, namely the Kogbetliantz (two-sided rotation) and the Hestenes (one- sided rotation) method. Kogbetliantz’s method has been considered, because it is suitable for mapping onto CORDIC array architecture and highly suitable for parallel computation. Here in its implementation, CORDIC algorithm provides the arithmetic units required in the processing elements as these enable the efficient implementation of plane rotation and phase computation. Many fundamental aspects of linear algebra rely on determining the rank of a matrix, making the SVD an important and widely used technique. DCT is one of the most widely used transform techniques in digital signal processing and it computation involves many multiplications and additions. The DCT based on CORDIC algorithm does not need multipliers. Moreover, it has regularity and simple architecture and it is used to compress a wide variety of images by transferring data into frequency domain. These digital signal-processing algorithms are used in many applications. The purpose of this thesis is to describe a solution in which a conventional CORDIC system is used to implement an SVD and DCT processing elements. The approach presented combines the low circuit complexity with high performance

ASIC implementation of FFT Engine for Audio Driver

Dynamic performance of the audio system is characterized by the parameters, SNR, SNDR, THD, SFDR and DC Componentin the signal. By measuring these parameters dynamically, suitable action can be taken to maintain these parameters within its limited value. This will increase the dynamic performance of audio system. The thesis work is divided into five parts, first is modeling of entire system in MATLAB and selecting the suitable algorithms to compute FFT and different dynamic parameters (SNR, SFDR, THD, SNDR, Percent THD plus Noise, DC component), second is making a top level model in Simulink in hardware prospective where we can replace each algorithm with corresponding block consisting of required hardware, third is making the entire top level model from floating point model to fixed point model where we can decide the processing capacity and data width of each hardware (A fixed point model a design in MATLAB is very close to a RTL model of a Digital design ), fourth step is to generate a synthesizable Verilog code using MATLAB HDL Coder for entire top model and final step is verification of generated RTL model in ModelSim by comparing it with standard MATLAB results. Our final aim is to design the system for Audio driver application which range is 20 Hz to 20 kHz, since we can verify the the system more accurately if we consider the whole range of frequency bin (zero to half of the sampling Frequency) so we have designed to desperate model, one for audio range and another for full range. Designed system can accurately measure 100 dB SNDR (based on observation). FFT engine has been designed for 65536 points (216 points) and input data width is 16 bit. Internal structure of FFT engine is designed to process 32 bit data. Fixed point algorithm is completely parametrized ( Except few miner changes in CORDIC block) for input data width. We can also increase the number of FFT points, but it will increase the requirement of RAM. There is a huge high level resource utilization in comparison to HDL optimized FFT block given by MATLAB. Number of required multipliers is almost half of HDL, and only two RAMs (65536 x 32 bit) is required to implement the entire system where only HDL optimized FFT block itself needs 34 RAMs of different sizes including two 65536 x 32 bit RAMs. We are using CORDIC algorithm to implement CORDIC multiplier, Absolute block and Logarithmic block. Due to the use of CORDIC multiplier there is no need of real multipliers (except angle multipliers) in CORDIC butterfly and also there is no need to store the twiddle factors in separate ROMs

Efficient arithmetic for high speed DSP implementation on FPGAs

The author was sponsored by EnTegra Ltd, a company who develop hardware and software products and services for the real time implementation of DSP and RF systems. The field programmable gate array (FPGA) is being used increasingly in the field of DSP. This is due to the fact that the parallel computing power of such devices is ideal for today’s truly demanding DSP algorithms. Algorithms such as the QR-RLS update are computationally intensive and must be carried out at extremely high speeds (MHz). This means that the DSP processor is simply not an option. ASICs can be used but the expense of developing custom logic is prohibitive. The increased use of the FPGA in DSP means that there is a significant requirement for efficient arithmetic cores that utilises the resources on such devices. This thesis presents the research and development effort that was carried out to produce fixed point division and square root cores for use in a new Electronic Design Automation (EDA) tool for EnTegra, which is targeted at FPGA implementation of DSP systems. Further to this, a new technique for predicting the accuracy of CORDIC systems computing vector magnitudes and cosines/sines is presented. This work allows the most efficient CORDIC design for a specified level of accuracy to be found quickly and easily without the need to run lengthy simulations, as was the case before. The CORDIC algorithm is a technique using mainly shifts and additions to compute many arithmetic functions and is thus ideal for FPGA implementation

Introduction to FPGA design

This paper presents an introduction to digital hardware design using Field Programmable Gate Arrays (FPGAs). After a historical introduction and a quick overview of digital design, the internal structure of a generic FPGA is discussed. We then describe the design flow, i.e., the steps needed to go from design idea to actual working hardware. Digital signal processing is an important area where FPGAs have found many applications in recent years. Therefore a complete section is devoted to this subject. The paper finishes with a discussion of important peripheral concepts essential for success in any project involving FPGAs