The GBT: A proposed architecure for multi-Gb/s data transmission in high energy physics

The future upgrade of the LHC accelerator, the SLHC, will increase the beam luminosity by a factor of ten leading to a corresponding growth of the amounts of data to be treated by the data transmission and acquisition systems. The development of the GBT chipset addresses this issue providing a means to increase the bandwidth available to transmit data to and from the counting room. The GigaBit Transceiver (GBT) architecture will provide the support to transmit simultaneously the three types of information required to run an experiment in a hostile radiation environment over a multipurpose link. This paper describes the GBT link architecture and some aspects of its implementation. As this project is still in the specification phase, detailed features might change prior to the final silicon fabrication

CMOS Integrated Circuits for Various Optical Applications

This chapter presents several CMOS integrated circuits (ICs) realized for various optical applications such as high-definition multimedia interface (HDMI), light detection and ranging (LiDAR), and Gigabit Ethernet (GbE). First, 4-channel 10-Gb/s per channel optical transmitter and receiver array chipset implemented in a 0.13-μm CMOS process are introduced to realize a 10-m active optical cable for HDMI 2.1 specifications. Second, a 16-channel optical receiver array chip is realized in a 0.18-μm CMOS technology for LiDAR applications. Third, a 40-GHz voltage-mode mirrored-cascode transimpedance amplifier (MC-TIA) is implemented in a 65-nm CMOS for a feasible 100-GbE application. Even with advanced nano-CMOS technologies, we have suggested novel circuit techniques for optimum performance, such as input data detection (IDD) for low power, feedforward and asymmetric preemphasis for high speed, double-gain feedforward for high gain, selectable equalizer (SEQ) for specific bandwidth, mirrored-cascode for fully differential topology, etc. We believe that these novel circuit techniques help to achieve low-cost, low-power solutions for various optical applications

Integrated Transversal Equalizers in High-Speed Fiber-Optic Systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-µm SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-µm multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10^-5 to less than 10^-12

Fast synchronization 3R burst-mode receivers for passive optical networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed

Toward a Gigabit Wireless Communications System

This paper presents the design and the realization of a hybrid wireless Gigabit Ethernet indoor communications system operating at 60 GHz. As the 60 GHz radio link operates only in a single-room configuration, an additional Radio over Fiber (RoF) link is used to ensure the communications within all the rooms of a residential environment. The system uses low complexity baseband processing modules. A byte synchronization technique is designed to provide a high value of the preamble detection probability and a very small value of the false detection probability. Conventional RS (255, 239) encoder and decoder are used for channel forward error correction (FEC). The FEC parameters are determined by the tradeoff between higher coding gain and hardware complexity. The results of bit error rate measurements at 875 Mbps are presented for various antennas configurations

100 Gbit/s serial transmission using a silicon-organic hybrid (SOH) modulator and a duobinary driver IC

100 Gbit/s three-level (50 Gbit/s 00K) signals are generated using a silicon-organic hybrid modulator and a BiCMOS duobinary driver IC at a BER of 8.5x10(-5)(<10(-12)). We demonstrate dispersion-compensated transmission over 5 km

100 Gbit/s serial transmission using a silicon-organic hybrid (SOH) modulator and a duobinary driver IC

100 Gbit/s three-level (50 Gbit/s 00K) signals are generated using a silicon-organic hybrid modulator and a BiCMOS duobinary driver IC at a BER of 8.5x10(-5)(<10(-12)). We demonstrate dispersion-compensated transmission over 5 km

A VME-based readout system for the CMS Preshower sub-detector

The CMS preshower is a fine grain detector that comprises 4288 silicon sensors, each containing 32 strips. The raw data are transferred from the detector to the counting room via 1208 optical fibres. Each fibre carries a 600-byte data packet per event. The maximum average level-1 trigger rate of 100 kHz results in a total data flow of ~72 GB/s from the preshower. For the readout of the preshower, 56 links to the CMS DAQ have been reserved, each having a bandwidth of 200 MB/s (2 kB/event). The total available downstream bandwidth of GB/s necessitates a reduction in the data volume by a factor of at least 7. A modular VME-based system is currently under development. The main objective of each VME board in this system is to acquire on-detector data from at least 22 optical links, perform on-line data reduction and pass the concentrated data to the CMS DAQ. The principle modules that the system is based on are being developed in collaboration with the TOTEM experiment

The TOTEM front end driver, its components and applications in the TOTEM experiment

The TOTEM Front End Driver, so-called TOTFED, receives and handles trigger building and tracking data from the TOTEM detectors, and interfaces to the global trigger and data acquisition systems. The TOTFED is based on the VME64x standard and has deliberately been kept modular. It is very flexible and programmable to deal with the different TOTEM sub-detectors and possible evolution of the data treatment and trigger algorithms over the duration of the experiment. The main objectives for each unit are to acquire ondetector data from up to 36 optical links, to perform fast data treatment (reduction, consistency checking, etc.), to transfer it to the next level of the system (via the Slink64 interface), and to store data on request for slow spy readout via VME64x or USB2.0. The TOTFED is fully compatible with CMS and permits TOTEM to run both standalone and together with CMS. The TOTEM Front End Driver, its components and applications in the TOTEM experiment are presented in this paper

Design & Implementation of PCI Express BUS Physical layer using VHDL

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