CMOS image sensor

A CMOS image sensor 101 comprises an active layer 11 of a first conductivity type arranged to be reversed biased and a pixel 20 comprising a photosensitive element comprising a well 22 of a second conductivity type and a well 21 of the first conductivity type containing active CMOS elements for reading and resetting the photosensitive element. The CMOS image sensor further comprises a doped buried layer 111 of the second conductivity type in the active layer beneath the well of the first conductivity type. The buried layer is arranged to extend a depletion region below the well of the second conductivity type also below the well of the first conductivity type

A high dynamic range digital LinLog CMOS image sensor architecture based on Event Readout of pixels and suitable for low voltage operation

Several approaches have been developed to extend the dynamic range of image sensor in order to keep all the information content of natural scenes covering a very broad range of illumination. Digital CMOS image sensor are especially well suited to wide dynamic range imaging by implementing dual sampling, multiple exposure methods using either column or in pixel ADC, or Address Event Representation. A new architecture of digital high dynamic range CMOS image sensor, suitable for low voltage operation, has been developed that implements a built-in dynamic compression function targeted to LinLog behavior, by combining an event based readout of pixels, the use of multiple integrations per frame and the coding of pixel values using the mantissa-exponent principle, to achieve the dynamic range extension

Gain Error Correction for CMOS Image Sensor Using Delta-Sigma Modulation

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. This includes lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADC is required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset error in its transfer function, which will lead to fix pattern noise. Correcting these gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. Therefore, a technique to minimize the effects of gain error in a delta-sigma modulation ADC for CMOS image sensor is discussed

RTS noise reduction of CMOS image sensors using amplifier-selection pixels

This paper describes a RTS (random telegraph signal) noise reduction technique for an active pixel CMOS image sensor (CIS) with in-pixel selectable dual source-follower amplifiers. In this CMOS image sensor, the lower-noise transistor in each pixel is selected in the readout operation using a table of determining the lower-noise transistors of all the pixels. A prototype image sensor with 65×290 pixels for demonstrating the effectiveness of this technique has been implemented using 0.18µm CMOS image sensor technology with pinned photodiode option. The measured result shows that the maximum noise using the amplifier-selection technique is reduced to 9.6e- from 17.2e- which is the maximum noise of the image array using one of two amplifiers in each pixel without selection

Development of high-performances monolithic CMOS detectors for space applications

This paper describes the development of a 750x750 pixels CMOS image sensor for star tracker applications. A first demonstrator of such a star tracker called SSM star tracker built around a 512x512 detector has been recently developed and proves the feasibility of such instrument. In order to take fully advantage of the CMOS image sensor step, the 750x750 device called SSM CMOS detector which will take part of the final star tracker, can be considered as a major technical breakthrough that gives a decisive advantage in terms of on satellite implementation cost and flexibility (sensor mass and power consumption minimisation, electronics and architecture flexibility). Indeed, built using the 0.5μm Alcatel Microelectronics standard CMOS technology, the SSM CMOS detector will feature on-chip temperature sensor and on-chip sequencer. In order to evaluate the radiation tolerance of such manufacturing technology, a radiation campaign that contains studies of total dose and latch-up effects has been led on a specific test vehicle

Radiation Effects on CMOS Image Sensors With Sub-2 µm Pinned Photodiodes

CMOS image sensor hardness under irradiation is a key parameter for application fields such as space or medical. In this paper, four commercial sensors featuring different technological characteristics (pitch, isolation or buried oxide) have been irradiated with 60Co source. Based on dark current and temporal noise analysis, we develop and propose a phenomenological model to explain pixel performance degradation

Smart CMOS image sensor for lightning detection and imaging

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach

Pixel design and evaluation in CMOS image sensor technology

A chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor (APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses. Besides, structures to study the influence of crosstalk between pixels have been incorporated

High Speed CMOS Image Sensor

abstract: High speed image sensors are used as a diagnostic tool to analyze high speed processes for industrial, automotive, defense and biomedical application. The high fame rate of these sensors, capture a series of images that enables the viewer to understand and analyze the high speed phenomena. However, the pixel readout circuits designed for these sensors with a high frame rate (100fps to 1 Mfps) have a very low fill factor which are less than 58%. For high speed operation, the exposure time is less and (or) the light intensity incident on the image sensor is less. This makes it difficult for the sensor to detect faint light signals and gives a lower limit on the signal levels being detected by the sensor. Moreover, the leakage paths in the pixel readout circuit also sets a limit on the signal level being detected. Therefore, the fill factor of the pixel should be maximized and the leakage currents in the readout circuits should be minimized. This thesis work presents the design of the pixel readout circuit suitable for high speed and low light imaging application. The circuit is an improvement to the 6T pixel readout architecture. The designed readout circuit minimizes the leakage currents in the circuit and detects light producing a signal level of 350µV at the cathode of the photodiode. A novel layout technique is used for the pixel, which improves the fill factor of the pixel to 64.625%. The read out circuit designed is an integral part of high speed image sensor, which is fabricated using a 0.18 µm CMOS technology with the die size of 3.1mm x 3.4 mm, the pixel size of 20µm x 20 µm, number of pixel of 96 x 96 and four 10-bit pipelined ADC’s. The image sensor achieves a high frame rate of 10508 fps and readout speed of 96 M pixels / sec.Dissertation/ThesisMasters Thesis Electrical Engineering 201

A High Throughput Lab-On-A-Chip System for Label Free Quantification of Breast Cancer Cells under Continuous Flow

This paper presents an LOC system combining microfluidic DEP channel with a CMOS image sensor for label and lens free detection and real-time counting of MCF-7 cells under continuous flow. Trapped and then released MCF-7 cells are accurately detected and counted under flow with a CMOS image sensor integrated underneath the DEP channel, for the first time in the literature. CMOS image sensor can capture 391 frames per second (fps) that allows detection of the released cells flowing through the channel with a flow rate up to 130 mu l/min (0.468 m/s). Therefore, the proposed system is able to detect the cells under high flow where conventional techniques for cell quantification such as fluorescent tagging become unusable. Detected cells are automatically counted with a computer program and the counting accuracy of the whole system is 95%. (C) 2016 The Authors. Published by Elsevier Ltd