CVM: Crossbar-based circuit Verification through Modeling

The implementation of Boolean functions using Nano crossbar-based switching lattices has been suggested as a substitute for conventional CMOS-based approaches in digital circuits. This alternative may satisfy the needs of future electronic designs, considering the expected end of Moore’s law. This study introduces CVM, a Crossbar-based circuit Verification through Modeling technique.Lattice Science Publication (LSP) © Copyright: All rights reserved

Logic synthesis and testing techniques for switching nano-crossbar arrays

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of â\u80\u9cEmerging Computing Modelsâ\u80\u9d or â\u80\u9cComputational Nanoelectronicsâ\u80\u9d, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS

Laser Induced Magnetization Reversal for Detection in Optical Interconnects

Optical interconnect has emerged as the front-runner to replace electrical interconnect especially for off-chip communication. However, a major drawback with optical interconnects is the need for photodetectors and amplifiers at the receiver, implemented usually by direct bandgap semiconductors and analog CMOS circuits, leading to large energy consumption and slow operating time. In this letter, we propose a new optical interconnect architecture that uses a magnetic tunnel junction (MTJ) at the receiver side that is switched by femtosecond laser pulses. The state of the MTJ can be sensed using simple digital CMOS latches, resulting in significant improvement in energy consumption. Moreover, magnetization in the MTJ can be switched on the picoseconds time-scale and our design can operate at a speed of 5 Gb/s for a single link

Asynchronous Nano-Electronics: Preliminary Investigation

This paper is a preliminary investigation in implementing asynchronous QDI logic in molecular nano-electronics, taking into account the restricted geometry, the lack of control on transistor strengths, the high timing variations. We show that the main building blocks of QDI logic can be successfully implemented; we illustrate the approach with the layout of an adder stage. The proposed techniques to improve the reliability of QDI apply to nano-CMOS as well

Implementing Boolean Functions with switching lattice networks

Four terminal switching network is an alternative structure to realize the logic functions in electronic circuit modeling. This network can be used to implement a Boolean function with less number of switches than the two terminal based CMOS switch. Each switch of the network is driven by a Boolean literal. Any switch is connected to its four neighbors if a literal takes the value 1 , else it is disconnected. In our work, we aimed to develop a technique by which we can find out if any Boolean function can be implemented with a given four-terminal network. It is done using the path of any given lattice network. First, we developed a synthesis tool by which we can create a library of Boolean functions with a given four-terminal switching network and random Boolean literals. This tool can be used to check the output of any lattice network which can also function as a lattice network solver. In the next step, we used the library functions to develop and test our MAPPING tool where the functions were given as input and from the output, we can get the implemented function in four terminal lattice network. Finally, we have proposed a systematic procedure to implement any Boolean function with a efficient way by any given one type of lattice network

Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose the Boolean functions according to generalizations of the classical Shannon decomposition, then generate the lattices for each component function, and finally implement the original function by a single composed lattice obtained by glueing together appropriately the lattices of the component functions. In particular we study the two decomposition schemes defining the bounded-level logic networks called P-circuits and EXOR-Projected Sums of Products (EP-SOPs). Experimental results show that about 34% of our benchmarks achieve a smaller area when implemented using the P-circuit decomposition for switching lattices, with an average gain of at least 25%, and about 27% of our benchmarks achieve a smaller area when implemented using the EP-SOP decomposition, with an average gain of at least 22%