A 1.8-V 4-ppm oC Reference Current with Process and Temperature

[[abstract]]A current reference generator with a proposed compensation circuit against temperature variation is presented. The current reference generator provides a reference current of 10 uA with temperature coefficient (TC) of 4 ppm/°C under temperature range from -40 to 125°C. The circuit occupies 0.008 mm2 in a 180-nm standard CMOS process.[[conferencetype]]國際[[conferencedate]]20130630~20130703[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Yeosu, Kore

A 0.82V supply and 23.4 ppm/0C current mirror assisted bandgap reference

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area

Estudio del diseño de un circuito de voltaje de referencia para aplicaciones de bajo voltaje y bajo consumo de energía

Este trabajo de investigación describe el funcionamiento de los circuitos que permiten la generación de un voltaje de referencia estable ante variaciones en la temperatura y el voltaje de alimentación. Las topologías clásicas de circuitos de voltaje de referencia limitan el voltaje que entregan a valores cercanos a 1.2 V, impidiendo que aplicaciones de menor voltaje puedan hacer uso de dichos circuitos. El principal inconveniente yace en que las topologías clásicas de estos circuitos limitan el voltaje que entregan a valores cercanos a 1.2 V. Actualmente muchos circuitos integrados se diseñan para operar con voltajes menores a 1.2 V, de modo que es necesario plantear las consideraciones que permitan el diseño de un circuito de voltaje de referencia de bajo voltaje. El propósito de este trabajo de investigación es exponer los fundamentos para el diseño de un circuito de voltaje de referencia. Se desarrolla la teoría que permite la obtención de un voltaje independiente de la temperatura. Posteriormente se analizan dos topologías: una convencional y otra de bajo voltaje. Esta última sirve de referencia para el diseño de voltaje de referencia de bajo voltaje. En la parte final de esta investigación se enuncian conclusiones sobre el marco teórico revisado. También se mencionan recomendaciones para el diseño de un circuito de bajo voltaje.Trabajo de investigació

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications

The instrumentation of radiation detectors for high energy physics calls for the development of very low-noise application-specific integrated-circuits and demanding system-level design strategies, with a particular focus on the minimisation of inter-ference noise from power anagement circuitry. On the other hand, the aggressive pixelisation of sensors and associated front-end electronics, and the high radiation exposure at the innermost tracking and vertex detectors, requires radiation-aware design and radiation-tolerant deep sub-micron CMOS technologies. This thesis explores circuit design techniques towards radiation tolerant power management integrated circuits, targeting applications on particle detectors and monitoring of accelerator-based experiments, aerospace and nuclear applications. It addresses advantages and caveats of commonly used radiation-hard layout techniques, which often employ Enclosed Layout or H-shaped transistors, in respect to the use of linear transistors. Radiation tolerant designs for bandgap circuits are discussed, and two different topologies were explored. A low quiescent current bandgap for sub-1 V CMOS circuits is proposed, where the use of diode-connected MOSFETs in weak-inversion is explored in order to increase its radiation tolerance. An any-load stable LDO architecture is proposed, and three versions of the design using different layout techniques were implemented and characterised. In addition, a switched DC-DC Buck converter is also studied. For reasons concerning testability and silicon area, the controller of the Buck converter is on-chip, while the inductance and the power transistors are left on-board. A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. The chip features Linear, ELT and H-shape LDO designs, bandgap circuits and a Buck DC-DC converter. We discuss the design, layout and test results of the prototype. The specifications in terms of voltage range and output current capability are based on the requirements set for the integrated on-detector electronics of the new CGEM-IT tracker for the BESIII detector. The thesis discusses the fundamental aspects of the proposed on-detector electronics and provides an in-depth depiction of the front-end design for the readout ASIC