Design Methodology of Very Large Scale Integration

Very Large Scale Integration (VLSI) deals with systems complexity rather than transistor size or circuit performance. VLSI design methodology is supported by Computer Aided Design (CAD) and Design Automation (DA) tools, which help VLSI designers to implement more complex and guaranteed designs. The increasing growth in VLSI complexity dictates a hierarchical design approach and the need for hardware DA tools. This paper discusses the generalized Design Procedure for CAD circuit design; the commercial CADs offered by CALMA and the Caesar System, supported by the Berkeley design tools. A complete design of a Content Addressable Memory (CAM) cell, using the Caesar system, supported by Berkeley CAD tools, is illustrated

Efficient algorithms for the constraint generation for integrated circuit layout compaction

A compactor for VLSI layouts is an essential component in many CAD systems for VLSI design. It reduces the area of a given layout violating any of the design rules dictated by the fabrication process. In many CAD systems for VLSI design the compacter generates a number of linear inequalities from the circuit layout. These so-called constraints restrict the coordinates of the layout components. The resulting inequality system is then solved in some optimum way. The solution of such inequality system can be done efficiently. The generation of the constraints, however, is a problem for which no efficient algorithms have been devised so far. We define the graph problem underlying the constraint generation for VLSI circuit compaction. Furthermore we develop efficient, i.e., O(nlogn) time algorithms for the generation of constraint systems that allow to change the layout topology during the conpaction in order to yield good compaction results, but at the same time are sparse enough to be solved efficiently, i.e., of size O(n). These algorithms are simple enough to be implemented

A systolic architecture for the correlation and accumulation of digital sequences

A fully systolic architecture for the implementation of digital sequence correlator/accumulators is described. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIX-Based Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processes of many types

DESIGN METHODOLOGIES AND SOME ASPECTS OF VLSI AND ULSI

This is a review and considers first technical aspects and drawbacks for realizing very large scale and wafer scale integrated circuits. Among these are small geometry effects and interconnection delay. Some solutions are considered. Next, design methodologies for VLSI are discussed, considering the hierarchy of VLSI systems. Finally the influences for students education are remarked and a design system consisting of CAD tools for logic synthesis and simulation, network-and device simulation, automated layout generation and layout-verification are described

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

The Design of Standard Cell VLSI Circuits

There are basically three methods of designing Very Large Scale Integrated (VLSI) circuits; Gate Array, Standard Cell, and Full Custom. The objective of this research is to design a VLSI circuit using the Standard Cell approach. A prime requisite for a successful design of these circuits is an integrated Computer Aided Design (CAD) system. The chip design requirements for an integrated CAD system are developed and their interrelationships are presented. As VLSI circuits grow in complexity, the problem of how to test them becomes more difficult. Two methods for testing are defined: 1. Insertion within the system of which the chip is a part, and use of standard system test techniques. 2. Self-test circuitry built into the chip. These testing techniques were used in the VLSI circuit in this report

A knowledge-based approach to VLSI-design in an open CAD-environment

A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI technique can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge - strategic and task-specific - in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

© 2015 IEEE.Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

Survey of partitioning techniques in silicon compilation

In the silicon compilation design process, partitioning is usually the first problem to be investigated because partitioning algorithms form the backbone of many algorithms including: system synthesis, processor synthesis, floorplanning, and placement. In this survey, several partitioning techniques will be examined. In addition, this paper will review the partitioning algorithms used by synthesis systems at different design levels