A programmable BIST architecture for clusters of Multiple-Port SRAMs

This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures

Multiport memories are widely used as embedded cores in all communication system-on-chip devices. Due to their high complexity and very low accessibility, built-in self-test (BIST) is the most common solution implemented to test the different memories embedded in the system. This article presents a programmable BIST architecture based on a single microprogrammable BIST processor and a set of memory wrappers designed to simplify the test of a system containing a large number of distributed multiport memories of different sizes (number of bits, number of words), access protocols (asynchronous, synchronous), and timing

The walking robot project

A walking robot was designed, analyzed, and tested as an intelligent, mobile, and a terrain adaptive system. The robot's design was an application of existing technologies. The design of the six legs modified and combines well understood mechanisms and was optimized for performance, flexibility, and simplicity. The body design incorporated two tripods for walking stability and ease of turning. The electrical hardware design used modularity and distributed processing to drive the motors. The software design used feedback to coordinate the system and simple keystrokes to give commands. The walking machine can be easily adapted to hostile environments such as high radiation zones and alien terrain. The primary goal of the leg design was to create a leg capable of supporting a robot's body and electrical hardware while walking or performing desired tasks, namely those required for planetary exploration. The leg designers intent was to study the maximum amount of flexibility and maneuverability achievable by the simplest and lightest leg design. The main constraints for the leg design were leg kinematics, ease of assembly, degrees of freedom, number of motors, overall size, and weight

Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip

Every new node of semiconductor technologies provides further miniaturization and higher performances, increasing the number of advanced functions that electronic products can offer. Silicon area is now so cheap that industries can integrate in a single chip usually referred to as System-on-Chip (SoC), all the components and functions that historically were placed on a hardware board. Although adding such advanced functionality can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies (0.13 micron and below) have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. Being able to rapidly develop, manufacture, test, diagnose and verify such complex new chips and products is crucial for the continued success of our economy at-large. This trend is expected to continue at least for the next ten years making possible the design and production of 100 million transistor chips. To speed up the research, the National Technology Roadmap for Semiconductors identified in 1997 a number of major hurdles to be overcome. Some of these hurdles are related to test and dependability. Test is one of the most critical tasks in the semiconductor production process where Integrated Circuits (ICs) are tested several times starting from the wafer probing to the end of production test. Test is not only necessary to assure fault free devices but it also plays a key role in analyzing defects in the manufacturing process. This last point has high relevance since increasing time-to-market pressure on semiconductor fabrication often forces foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. The feedback derived from test is the only way to analyze and isolate many of the defects in today’s processes and to increase process’s yield. With the increasing need of high quality electronic products, at each new physical assembly level, such as board and system assembly, test is used for debugging, diagnosing and repairing the sub-assemblies in their new environment. Similarly, the increasing reliability, availability and serviceability requirements, lead the users of high-end products performing periodic tests in the field throughout the full life cycle. To allow advancements in each one of the above scaling trends, fundamental changes are expected to emerge in different Integrated Circuits (ICs) realization disciplines such as IC design, packaging and silicon process. These changes have a direct impact on test methods, tools and equipment. Conventional test equipment and methodologies will be inadequate to assure high quality levels. On chip specialized block dedicated to test, usually referred to as Infrastructure IP (Intellectual Property), need to be developed and included in the new complex designs to assure that new chips will be adequately tested, diagnosed, measured, debugged and even sometimes repaired. In this thesis, some of the scaling trends in designing new complex SoCs will be analyzed one at a time, observing their implications on test and identifying the key hurdles/challenges to be addressed. The goal of the remaining of the thesis is the presentation of possible solutions. It is not sufficient to address just one of the challenges; all must be met at the same time to fulfill the market requirements

A LOW-COST ROBOT CONTROLLER AND ITS SOFTWARE PROBLEMS

In recent years the need for advanced robot control algorithms for industrial robots has grown. The deyelopment of a low-cost robot controller to support the development, implementation and testing of those algorithms which require high computational power was targeted. This paper deals wiith the requirements of an experimental controller that can be connected to a NOKIA PUMA 560 robot arm. It explains the IBM PC compatible host and the TEXAS Digital Signal Processor (DSP) based hardware. On the host computer the UNIX-like QXX real-time operating system is used. In the current phase of development the robot controller works with the classical decentralised joint control based strategy. The Advanced Robot Pogramming System (ARPS) explicit robot programming, language is implementedl

Arctic Standards: Recommendations on Oil Spill Prevention, Response, and Safety in the U.S. Arctic Ocean

Oil spilled in Arctic waters would be particularly difficult to remove. Current technology has not been proved to effectively clean up oil when mixed with ice or when trapped under ice. An oil spill would have a profoundly adverse impact on the rich and complex ecosystem found nowhere else in the United States. The Arctic Ocean is home to bowhead, beluga, and gray whales; walruses; polar bears; and other magnificent marine mammals, as well as millions of migratory birds. A healthy ocean is important for these species and integral to the continuation of hunting and fishing traditions practiced by Alaska Native communities for thousands of years.To aid the United States in its efforts to modernize Arctic technology and equipment standards, this report examines the fierce Arctic conditions in which offshore oil and gas operations could take place and then offers a summary of key recommendations for the Interior Department to consider as it develops world-class, Arctic-specific regulatory standards for these activities. Pew's recommendations call for improved technology,equipment, and procedural requirements that match the challenging conditions in the Arctic and for full public participation and transparency throughout the decision-making process. Pew is not opposed to offshore drilling, but a balance must be achieved between responsible energy development and protection of the environment.It is essential that appropriate standards be in place for safety and for oil spill prevention and response in this extreme, remote, and vulnerable ecosystem. This report recommends updating regulations to include Arctic specific requirements and codifying temporary guidance into regulation. The appendixes to this report provide substantially more detail on the report's recommendations, including technical background documentation and additional referenced materials. Please refer to the full set of appendixes for a complete set of recommendations. This report and its appendixes offer guidelines for responsible hydrocarbon development in the U.S. Arctic Ocean

Tracing Fault Effects in FPGA Systems

The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets – SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.

Self-Healing Cellular Automata to Correct Soft Errors in Defective Embedded Program Memories

Static Random Access Memory (SRAM) cells in ultra-low power Integrated Circuits (ICs) based on nanoscale Complementary Metal Oxide Semiconductor (CMOS) devices are likely to be the most vulnerable to large-scale soft errors. Conventional error correction circuits may not be able to handle the distributed nature of such errors and are susceptible to soft errors themselves. In this thesis, a distributed error correction circuit called Self-Healing Cellular Automata (SHCA) that can repair itself is presented. A possible way to deploy a SHCA in a system of SRAM-based embedded program memories (ePM) for one type of chip multi-processors is also discussed. The SHCA is compared with conventional error correction approaches and its strengths and limitations are analyzed

On-board processing satellite network architecture and control study

The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures. Use of the following transmission architecture was considered: satellite switched TDMA; TDMA up, TDM down; scanning (hopping) beam TDMA; FDMA up, TDM down; satellite switched MF/TDMA; and switching Hub earth stations with double hop transmission. A candidate network architecture will be selected that: comprises multiple access subnetworks optimized for each user; interconnects the subnetworks by means of a baseband processor; and optimizes the marriage of interconnection and access techniques. An overall network control architecture will be provided that will serve the needs of the baseband and satellite switched RF interconnected subnetworks. The results of the studies shall be used to identify elements of network architecture and control that require the greatest degree of technology development to realize an operational system. This will be specified in terms of: requirements of the enabling technology; difference from the current available technology; and estimate of the development requirements needed to achieve an operational system. The results obtained for each of these tasks are presented