Elastic circuits

Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.Peer ReviewedPostprint (published version

Naturalized Communication and Testing

We ”naturalize” the handshake communication links of a self-timed system by assigning the capabilities of filling and draining a link and of storing its full or empty status to the link itself. This contrasts with assigning these capabilities to the joints, the modules connected by the links, as was previously done. Under naturalized communication, the differences between Micropipeline, GasP, Mousetrap, and Click circuits are seen only in the links — the joints become identical; past, present, and future link and joint designs become interchangeable. We also “naturalize” the actions of a self-timed system, giving actions status equal to states — for the purpose of silicon test and debug. We partner traditional scan test techniques dedicated to state with new test capabilities dedicated to action. To each and every joint, we add a novel proper-start-stop circuit, called MrGO, that permits or forbids the action of that joint. MrGO, pronounced “Mister GO,” makes it possible to (1) exit an initial state cleanly to start circuit operation in a delay-insensitive manner, (2) stop a running circuit in a clean and delay-insensitive manner, (3) single- or multi-step circuit operations for test and debug, and (4) test sub-systems at speed.We present a static control flow analysis used in the Simple Unified Policy Programming Language(Suppl) compiler to detect internally inconsistent policies. For example, an access control policy can decide to both “allow” and “deny” access for a user; such an inconsistency is called a conflict. Policies in Suppl. follow the Event-Condition-Action paradigm; predicates are used to model conditions and event handlers are written in an imperative way. The analysis is twofold; it first computes a superset of all conflicts by looking for a combination of actions in the event handlers that might violate a user-supplied definition of conflicts. SMT solvers are then used to try to rule out the combinations that cannot possibly be executed. The analysis is formally proven sound in Coq in the sense that no actual conflict will be ruled out by the SMT solvers. Finally, we explain how we try to show the user what causes the conflicts, to make them easier to solve

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Synthesis and Optimization of Pipelined Packet Processors

We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches

Designing an alkaline water electrolysis test bench

In this study, a design of an alkaline water electrolysis test bench is made for VTT. This design work includes making a complete process and instrumentation (P&I) diagram of the test bench, compiling two different safety analyses of the test bench, and finally choosing the necessary instruments according to both the safety analyses and the P&I diagram. Due to confidentiality reasons, the complete P&I diagram of the test bench is not provided in this study. The purpose of this study is to strengthen Finnish know-how in alkaline electrolysis, as Finland currently lacks extensive practical know-how of this technology at an industrial scale. Utilization of the test bench offers an opportunity for interested companies to be the technology’s forerunners, providing agreed research data and educating competent personnel. Interested companies can also utilize the test bench for stack testing and development purposes. This study is in the style of design research, which also partly involves some empirical research. The study presents the working principle of alkaline electrolysis, and the challenges encountered during the design work of the test bench. Literature and a previous P&I diagram from VTT’s earlier test bench have been used as help in the P&I diagram design. Empirical research has been used to illustrate the separation process of the two-phase flow to be able to evaluate the behavior and the amount of unwanted gas (H2 and O2) bubbles in real operating conditions. The safety analyzes performed during the design work have been made and documented according to the standards EN IEC 60079-10-1:2021, EN IEC 61511-1:2017 and EN IEC 61511-2:2017. The standards give instructions for classifying potentially explosive zones and how to ensure functional safety for the test bench. After this study, VTT has a straightforward plan on how to implement an alkaline electrolysis test bench, and what kind of modifications would be needed in different future situations. Moreover, this thesis work will provide VTT a complete list of selected and necessary instruments, and competent personnel to develop the test bench further. The study provides an overview of the measures still needed, after which the assembly and commissioning of the test bench can be started in the upcoming months.Tutkielmassa suunnitellaan alkalielektrolyysin testipenkki VTT:lle. Suunnittelutyö sisältää täydellisen prosessi- ja instrumentaatiokaavion (PI-kaavio) teon, kahden turvallisuusanalyysin laatimisen testipenkkiä varten, ja tarvittavien instrumenttien valinnan PI-kaavion ja turvallisuusanalyysien esittämien tarpeiden mukaisesti. Salassapitovelvollisuuden vuoksi täydellistä PI-kaaviota ei esitetä tässä tutkielmassa. Tutkielman tarkoitus on vahvistaa suomalaista osaamista alkalielektrolyysin parissa, sillä tällä hetkellä Suomesta puuttuu laaja alkalielektrolyysin käytännönläheinen osaaminen teollisuusmittakaavassa. Testipenkin käyttö tarjoaa kiinnostuneille yrityksille mahdollisuuden olla alan teknologian edelläkävijöitä, tarjoamalla etukäteen sovittua tutkimusdataa ja kouluttamalla osaavaa henkilökuntaa. Kiinnostuneet yritykset voivat myös hyödyntää testipenkkiä elektrolyysikennoston testaamiseen ja kehittämiseen. Tutkielma on kehittämistutkimuksen tyylinen, johon liittyy myös osittain kokeellista tutkimista. Tutkielmassa esitellään alkalielektrolyysin toimintatapa, ja kyseisen teknologian testipenkin suunnitteluvaiheen haasteet. Apuna PI-kaavion suunnittelussa on käytetty kirjallisuudesta saatavaa tietoa ja yhtä VTT:n aikaisemman testipenkin PI-kaaviota. Kokeellista tutkimusta on hyödynnetty kaksifaasivirtauksen erotuksen havainnollistamisessa, jotta pystytään arvioimaan haitallisten vety- ja happikaasukuplien käyttäytymistä ja määrä oikeassa tilanteessa. Suunnittelutyön aikana tehdyt turvallisuusanalyysit ovat laadittu ja dokumentoitu standardien EN IEC 60079-10-1:2021, EN IEC 61511-1:2017 ja EN IEC 61511-2:2017 mukaisesti. Standardit ohjeistavat räjähdysvaarallisten tilojen luokitteluun ja toiminnallisen turvallisuuden varmistamiseen. Tutkielman jälkeen VTT:llä on suoraviivainen suunnitelma, miten toteuttaa alkalielektrolyysin testipenkki, ja millaisia muokkauksia tämä tarvitsee tulevissa tilanteissa. Lisäksi tutkielma tarjoaa VTT:lle täydellisen listan valituista ja tarvittavista instrumenteista, ja teknologiaan perehtynyttä henkilöstöä kehittämään testipenkkiä pidemmälle. Tutkielma tarjoaa katsauksen vielä tarvittavista toimenpiteistä, joiden jälkeen testipenkin rakentamisen ja käyttöönoton voi aloittaa tulevina kuukausina

Analysis and Optimization for Pipelined Asynchronous Systems

Most microelectronic chips used today--in systems ranging from cell phones to desktop computers to supercomputers--operate in basically the same way: they synchronize the operation of their millions of internal components using a clock that is distributed globally. This global clocking is becoming a critical design challenge in the quest for building chips that offer increasingly greater functionality, higher speed, and better energy efficiency. As an alternative, asynchronous or clockless design obviates the need for global synchronization; instead, components operate concurrently and synchronize locally only when necessary. This dissertation focuses on one class of asynchronous circuits: application specific stream processing systems (i.e. those that take in a stream of data items and produce a stream of processed results.) High-speed stream processors are a natural match for many high-end applications, including 3D graphics rendering, image and video processing, digital filters and DSPs, cryptography, and networking processors. This dissertation aims to make the design, analysis, optimization, and testing of circuits in the chosen domain both fast and efficient. Although much of the groundwork has already been laid by years of past work, my work identifies and addresses four critical missing pieces: i) fast performance analysis for estimating the throughput of a fine-grained pipelined system; ii) automated and versatile design space exploration; iii) a full suite of circuit level modules that connect together to implement a wide variety of system behaviors; and iv) testing and design for testability techniques that identify and target the types of errors found only in high-speed pipelined asynchronous systems. I demonstrate these techniques on a number of examples, ranging from simple applications that allow for easy comparison to hand-designed alternatives to more complex systems, such as a JPEG encoder. I also demonstrate these techniques through the design and test of a fully asynchronous GCD demonstration chip