Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved

Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

ELECTROSTATIC DISCHARGE AND ELECTRICAL OVERSTRESS FAILURES OF NON-SILICON DEVICES

Electrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of advanced device technologies. This thesis provides a comprehensive understanding of ESD and EOS failures in GaAs and SiGe devices. In the first part of this thesis, characteristics of internal damage caused by several ESD test models and EOS stress in non-silicon devices (GaAs and SiGe) are identified. Failure signatures are correlated with field failures using various failure analysis techniques. The second part of this thesis discusses the effects of ESD latent damage in GaAs devices. Depending on the stress level, ESD voltage can causes latent failures if the device is repeatedly stressed under low ESD voltage conditions, and can cause premature damage leading eventually to catastrophic failures. Electrical degradation due to ESD-induced latent damage in GaAs MESFETs after cumulative low-level ESD stress is studied. Using failure analysis, combined with electrical characterization, the failure modes and signatures of EOS stressed devices with and without prior low-level ESD stress are compared. To predict the power-to-failure level of GaAs and silicon devices, an ESD failure model using a thermal RC network was developed. A correlation method of the real ESD stress and square wave pulse has been developed. The equivalent duration of the square pulse is calculated and proposed for the HBM ESD stress. The dependence of this value on the ESD stress level and material properties is presented as well

Stratégies de modélisation et protection vis à vis des décharges électrostatiques (ESD) adaptées aux exigences de la norme du composant chargé (CDM)

Dans l’industrie semiconducteur, une décharge électrostatique peut se produire tout au long de la vie d’une puce électronique, et constitue un vrai problème pour la fiabilité du circuit intégré et une cause majeure de défaillance. Un nouveau modèle, modèle du composant chargé (CDM, Charged Device Model) a été récemment développé pour simuler un composant chargé qui se décharge au travers d'une de ses broches vers la masse. La forme d’onde d’une telle décharge se présente comme une impulsion de courant de grande amplitude (15A pour un CDM de 1KV sur une capacité de charge de 10pF) d’une durée de seulement quelques nanosecondes. En effet, il est de plus en plus courant de constater des signatures de défaillance ESD au coeur des circuits intégrés, généralement des claquages d’oxyde qui sont typiquement induites par les décharges CDM. Une protection ESD ayant une dynamique de déclenchement inappropriée ou la circulation d'un fort courant de décharge (dans le substrat ou sur les pistes métalliques) peut induire localement des variations de potentiel suffisantes pour endommager les oxydes (3-5nm d’épaisseur pour la technologie CMOS 45nm). Face aux défis de la décharge CDM, dans cette thèse, nous nous sommes intéressée d’abord à la détection et la compréhension des défauts latents induits par les stress CDM dans les circuits intégrés, en utilisant une technique de haute sensibilité, « la mesure de bruit en basse fréquence ». Un convertisseur DC-DC a été stressé par le test CDM, après chaque étape de traitement (stockage, recuit, et vieillissement), et l’évolution des défauts latents générés a été étudiée. Ensuite, nous avons proposé une méthodologie de modélisation du circuit intégré complet afin de simuler la stratégie de protection vis-à-vis des stress CDM en limitant les problèmes de convergence de simulation. Son originalité réside dans la modélisation de la résistance du substrat en très forte injection adaptée à la décharge CDM à l’aide de la mesure VF-TLP (Very Fast Transmission Line Pulsing) et de la simulation physique 2D et 3D. La méthodologie a été validée sur une technologie CMOS avancée 45nm et une technologie BiCMOS 0,25mm). A la fin, la méthodologie de simulation CDM a été validée sur un produit commercial. ABSTRACT : In the semiconductor industry, electrostatic discharge (ESD) can occur throughout over the whole life of a chip. This is a real problem for the reliability of the integrated circuit (IC) and a major failure cause. A new ESD model, Charged Device Model (CDM) was recently developed to simulate a charged device which discharges through one of its pin to ground. The waveform of such a discharge is a current pulse of high amplitude (15A for a 1KV CDM stress on a precharged capacitor of 10pF) over a few nanoseconds duration. Indeed, it is increasingly common to encounter ESD failure signatures into the IC core, usually gate oxide breakdowns that are typically induced by CDM stress. ESD protections with inappropriate triggering speed or strong discharge currents (into the substrate or the metal tracks) can locally lead to potential drop sufficient to damage the oxide (3-5nm thickness in 45nm CMOS technology).Given the challenges of the CDM discharges, this thesis was firstly focused on the detection and understanding of latent defects caused by CDM stress in integrated circuits, using a high- ensitivity technique, namely low frequency noise measurement (LFN). A DCDC converter has been stressed by the CDM test. After each step of processing (storage, burn-in, and aging), the evolution of latent defects generated was investigated. Secondly, a methodology for modeling the complete integrated circuit has been proposed to simulate the CDM protection strategy by limiting the simulation convergence problems. Its main originality consists in the modeling of the substrate resistance under very high injection adapted to the CDM discharge using both VF-TLP (Very Fast Transmission Line Pulsing) measurement and 2D/3D physical simulation. The model was successfully validated on 45nm CMOS and 0.25 μm BiCMOS technologies. Finally, the CDM simulation methodology was validated on a commercial product

Design, Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier (scr)-based Devices For Electrostatic Discha

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives

Low-Leakage ESD Power Supply Clamps in General Purpose 65 nm CMOS Technology

Electrostatic discharge (ESD) is a well-known contributor that reduces the reliability and yield of the integrated circuits (ICs). As ICs become more complex, they are increasingly susceptible to such failures due to the scaling of physical dimensions of devices and interconnect on a chip [1]. These failures are caused by excessive electric field and/or excessive current densities and result in the dielectric breakdown, electromigration of metal lines and contacts. ESD can affect the IC in its different life stages, from wafer fabrication process to failure in the field. Furthermore, ESD events can damage the integrated circuit permanently (hard failure), or cause a latent damage (soft failure) [2]. ESD protection circuits consisting of I/O protection and ESD power supply clamps are routinely used in ICs to protect them against ESD damage. The main objective of the ESD protection circuit is to provide a low-resistive discharge path between any two pins of the chip to harmlessly discharge ESD energy without damaging the sensitive circuits. The main target of this thesis is to design ESD power supply clamps that have the lowest possible leakage current without degrading the ESD protection ability in general purpose TSMC 65 nm CMOS technology. ESD clamps should have a very low-leakage current and should be stable and immune to the power supply noise under the normal operating conditions of the circuit core. Also, the ESD clamps must be able to handle high currents under an ESD event. All designs published in the general purpose 65 nm CMOS technology have used the SCR as the clamping element since the SCR has a higher current carrying capability compared to an MOS transistor of the same area [3]. The ESD power supply clamp should provide a low-resistive path in both directions to be able to deal with both PSD and NDS zapping modes. The SCR based design does not provide the best ESD protection for the NDS zapping mode (positive ESD stress at VSS with grounded VDD node) since it has two parasitic resistances (RNwell and RPsub) and one parasitic diode (the collector to base junction diode of the PNP transistor) in the path from the VSS to VDD. Furthermore, SCR-based designs are not suitable for application that exposed to hot switching or ionizing radiation [2]. In GP process, the gate oxide thickness of core transistors is reduced compared with LP process counterpart to achieve higher performance designs for high-frequency applications using 1 V core transistors and 2.5 V I/O option. The thinner gate oxide layer results in higher leakage current due to gate tunneling [4]. Therefore, using large thin oxide MOS transistors as clamping elements will result in a huge leakage. In this thesis, four power supply ESD clamps are proposed in which thick oxide MOS transistors are used as the main clamping element. Therefore, the low-leakage current feature is achieved without significantly degrading the ESD performance. In addition, the parasitic diode of the MOS transistors provides the protection against NSD-mode. In this thesis, two different ESD power supply clamp architectures are proposed: standalone ESD power supply clamps and hybrid ESD power supply clamps. Two standalone clamps are proposed: a transient PMOS based ESD clamp with thyristor delay element (PTC), and a static diode triggered power supply (DTC). The standalone clamps were designed to protect the circuit core against ±125 V CDM stress by limiting the voltage between the two power rails to less than the oxide breakdown voltage of the core transistors, BVOXESD = 5 V. The large area of this architecture was the price for maintaining the low-leakage current and an adequate ESD protection. The hybrid clamp architecture was proposed to provide a higher ESD protection, against ±300 V CDM stress, while reducing the layout area and maintaining the low-leakage feature. In the hybrid clamp structure, two clamps are connected in parallel between the two power supply rails, a static clamp, and a transient clamp. The static clamp triggers first and starts to sink the ESD energy and then an RC network triggers the primary transient clamp to sink most of the ESD stress. Two hybrid designs were proposed: PMOS ESD power supply clamp with thyristor delay element and diodes (PTDC), and NMOS ESD power supply clamp with level shifter delay element and diode (NLDC). Simulation results show that the proposed clamps are capable of protecting the circuit core against ±1.5 kV HBM and at least against ±125 V CDM stresses. The measurement results show that all of the proposed clamps are immune against false triggering, and transient induced latch-up. Furthermore, all four designs have responded favorably to the 4 V ESD-like pulse voltage under both chip powered and not powered conditions and after the stress ends the designs turned off. Finally, TLP measurement results show that all four proposed designs meet the minimum design requirement of the ESD protection circuit in the 65 nm CMOS technology (i.e. HBM protection level of ±1.5 kV )

Reliability Analysis of Nanocrystal Embedded High-k Nonvolatile Memories

The evolution of the MOSFET technology has been driven by the aggressive shrinkage of the device size to improve the device performance and to increase the circuit density. Currently, many research demonstrated that the continuous polycrystalline silicon film in the floating-gate dielectric could be replaced with nanocrystal (nc) embedded high-k thin film to minimize the charge loss due to the defective thin tunnel dielectric layer. This research deals with both the statistical aspect of reliability and electrical aspect of reliability characterization as well. In this study, the Zr-doped HfO2 (ZrHfO) high-k MOS capacitors, which separately contain the nanocrystalline zinc oxide (nc-ZnO), silicon (nc-Si), Indium Tin Oxide (nc-ITO) and ruthenium (nc-Ru) are studied on their memory properties, charge transportation mechanism, ramp-relax test, accelerated life tests, failure rate estimation and thermal effect on the above reliability properties. C-V hysteresis result show that the amount of charges trapped in nanocrystal embedded films is in the order of nc-ZnO\u3enc-Ru\u3enc-Si~nc-ITO, which might probably be influenced by the EOT of each sample. In addition, all the results show that the nc-ZnO embedded ZrHfO non-volatile memory capacitor has the best memory property and reliability. In this study, the optimal burn-in time for this kind of device has been also investigated with nonparametric Bayesian analysis. The results show the optimal burn-in period for nc-ZnO embedded high-k device is 5470s with the maximum one-year mission reliability