92 research outputs found
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.Junta de Andalucía P09-TIC-5386Gobierno Español TEC2011-2830
Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters
The evaluation of the linearity performance of a high resolution Analog-to-
Digital Converter (ADC) by the Standard Histogram method is an outstanding
challenge due to the requirement of high purity of the input signal and
the high number of output data that must be acquired to obtain an acceptable
accuracy on the estimation. These requirements become major application
drawbacks when the measures have to be performed multiple times
within long test flows and for many parts, and under an industrial environment
that seeks to reduce costs and lead times as is the case in the New
Space sector. This thesis introduces two alternative methods that succeed
in relaxing the two previous requirements for the estimation of the Integral
Nonlinearity (INL) parameter in ADCs. The methods have been evaluated
by estimating the Integral Non-Linearity pattern by simulation using realistic
high-resolution ADC models and experimentally by applying them to real
high performance ADCs.
First, the challenge of applying the Standard Histogram method for the
evaluation of static parameters in high resolution ADCs and how the drawbacks
are accentuated in the New Space industry is analysed, being a highly
expensive method for an industrial environment where cost and lead time
reduction is demanded. Several alternative methods to the Standard Histogram
for estimating Integral Nonlinearity in high resolution ADCs are reviewed
and studied. As the number of existing works in the literature is very
large and addressing all of them is a challenge in itself, only those most relevant
to the development of this thesis have been included. Methods based
on spectral processing to reduce the number of data acquired for the linearity
test and methods based on a double histogram to be able to use generators
that do not meet the the purity requirement against the ADC to be tested are
further analysed.
Two novel contributions are presented in this work for the estimation of
the Integral Nonlinearity in ADCs, as possible alternatives to the Standard
Histogram method. The first method, referred to as SSA (Simple Spectral Approach),
seeks to reduce the number of output data that need to be acquired
and focuses on INL estimation using an algorithm based on processing the
spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard
Histogram method, although the estimation accuracy will depend on
how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm
cannot be used to perform a calibration of the ADC nonlinearity error,
but it can be applied to find out between which limits it lies and what its
approximate shape is. The second method, named SDH (Simplified Double
Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity
generator. The approach uses two histograms constructed from the
two set of output data in response to two identical input signals except for a
dc offset between them. Using a simple adder model, an extended approach
named ESDH (Extended Simplified Double Histogram) addresses and corrects
for possible time drifts during the two data acquisitions, so that it can
be successfully applied in a non-stationary test environment. According to
the experimental results obtained, the proposed algorithm achieves high estimation
accuracy.
Both contributions have been successfully tested in high-resolution ADCs
with both simulated and real laboratory experiments, the latter using a commercial
ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from
Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital
(ADC) de alta resolución mediante el método estándar del Histograma
constituye un gran desafío debido los requisitos de alta pureza de la señal
de entrada y del elevado número de datos de salida que deben adquirirse
para obtener una precisión aceptable en la estimación. Estos requisitos encuentran
importantes inconvenientes para su aplicación cuando las medidas
deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un
gran número de piezas, y todo bajo un entorno industrial que busca reducir
costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta
tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos
anteriores para la estimación de los parámetros de no linealidad en los
ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad
Integral (INL) mediante simulación utilizando modelos realistas de ADC de
alta resolución y experimentalmente aplicándolos en ADCs reales.
Inicialmente se analiza el reto que supone la aplicación del método estándar
del Histograma para la evaluación de los parámetros estáticos en ADCs
de alta resolución y cómo sus inconvenientes se acentúan en la industria del
Nuevo Espacio, siendo un método altamente costoso para un entorno industrial
donde se exige la reducción de costes y plazos de entrega. Se estudian
métodos alternativos al Histograma estándar para la estimación de la No Linealidad
Integral en ADCs de alta resolución. Como el número de trabajos es
muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos
más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número
de datos que necesitan ser adquiridos y los métodos basados en un doble
histograma para poder utilizar generadores que no cumplen el requisito de
precisión frente al ADC a medir.
En este trabajo se presentan dos novedosas aportaciones para la estimación
de la No Linealidad Integral en ADCs, como posibles alternativas al método
estándar del Histograma. El primer método, denominado SSA (Simple Spectral
Approach), busca reducir el número de datos de salida que es necesario
adquirir y se centra en la estimación de la INL mediante un algoritmo basado
en el procesamiento del espectro de la señal de salida cuando se utiliza un
estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número
mucho menor de muestras que el método estándar del Histograma, aunque
la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón
de no-linealidad del ADC a medir. En general, este algoritmo no puede
utilizarse para realizar una calibración del error de no linealidad del ADC,
pero puede aplicarse para averiguar entre qué límites se encuentra y cuál
es su forma aproximada. El segundo método, denominado SDH (Simplified
Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando
un generador de baja pureza. El algoritmo utiliza dos histogramas,
construidos a partir de dos conjuntos de datos de salida en respuesta a dos
señales de entrada idénticas, excepto por un desplazamiento constante entre
ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado
ESDH (Extended Simplified Double Histogram) aborda y corrige
las posibles derivas temporales durante las dos adquisiciones de datos, de
modo que puede aplicarse con éxito en un entorno de prueba no estacionario.
De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto
alcanza una alta precisión de estimación.
Ambas contribuciones han sido probadas en ADCs de alta resolución
con experimentos tanto simulados como reales en laboratorio, estos últimos
utilizando un ADC comercial con una resolución de 14 bits y una tasa de
muestreo de 65Msps (AD6644 de Analog Devices)
Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs
This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account.
In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected.
The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration
Design and debugging of multi-step analog to digital converters
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process
Analysis and design of low-power data converters
In a large number of applications the signal processing is done exploiting both
analog and digital signal processing techniques. In the past digital and analog
circuits were made on separate chip in order to limit the interference and other
side effects, but the actual trend is to realize the whole elaboration chain on a
single System on Chip (SoC). This choice is driven by different reasons such as the
reduction of power consumption, less silicon area occupation on the chip and also
reliability and repeatability. Commonly a large area in a SoC is occupied by digital
circuits, then, usually a CMOS short-channel technological processes optimized to
realize digital circuits is chosen to maximize the performance of the Digital Signal
Proccessor (DSP). Opposite, the short-channel technology nodes do not represent
the best choice for analog circuits. But in a large number of applications, the signals
which are treated have analog nature (microphone, speaker, antenna, accelerometers,
biopotential, etc.), then the input and output interfaces of the processing chip are
analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC)
both digital and analog circuits can be found. This gives advantages in term of total
size, cost and power consumption of the SoC. The specific characteristics of CMOS
short-channel processes such as:
• Low breakdown voltage (BV) gives a power supply limit (about 1.2 V).
• High threshold voltage VTH (compared with the available voltage supply) fixed
in order to limit the leakage power consumption in digital applications (of the
order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many
problems with the stacked topologies.
• Threshold voltage dependent on the channel length VTH = f(L) (short channel
effects).
• Low value of the output resistance of the MOS (r0) and gm limited by speed
saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20
to 26dB.
• Mismatch which brings offset effects on analog circuits.
make the design of high performance analog circuits very difficult. Realizing lowpower
circuits is fundamental in different contexts, and for different reasons: lowering
the power dissipation gives the capability to reduce the batteries size in mobile
devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the
life of remote sensing devices, satellites, space probes, also allows the reduction of
the size and weight of the heat sink. The reduction of power dissipation allows the
realization of implantable biomedical devices that do not damage biological tissue.
For this reason, the analysis and design of low power and high precision analog
circuits is important in order to obtain high performance in technological processes
that are not optimized for such applications. Different ways can be taken to reduce
the effect of the problems related to the technology:
• Circuital level: a circuit-level intervention is possible to solve a specific problem
of the circuit (i.e. Techniques for bandwidth expansion, increase the gain,
power reduction, etc.).
• Digital calibration: it is the highest level to intervene, and generally going to
correct the non-ideal structure through a digital processing, these aims are
based on models of specific errors of the structure.
• Definition of new paradigms.
This work has focused the attention on a very useful mixed-signal circuit: the
pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in
high-precision applications where a resolution of about 10-16 bits and sampling
rates above hundreds of Mega-samples per second (telecommunication, radar, etc.)
are needed. An introduction on the theory of pipeline ADC, its state of the art
and the principal non-idealities that affect the energy efficiency and the accuracy
of this kind of data converters are reported in Chapter 1. Special consideration is
put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep
submicron technology nodes side effects called short channel effects exist opposed to
older technology nodes where undesired effects are not present. An overview of the
short channel effects and their consequences on design, and also power consuption
reduction techniques, with particular emphasis on the specific techniques adopted
in pipelined ADC are reported in Chapter 2. Moreover, another way may be
undertaken to increase the accuracy and the efficiency of an ADC, this way is the
digital calibration. In Chapter 3 an overview on digital calibration techniques, and
furthermore a new calibration technique based on Volterra kernels are reported. In
some specific applications, such as software defined radios or micropower sensor,
some circuits should be reconfigurable to be suitable for different radio standard
or process signals with different charateristics. One of this building blocks is the
ADC that should be able to reconfigure the resolution and conversion frequency. A
reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply
starting from the required conversion frequency was developed, and the results are
reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for
the feedback loop and its theory is described
Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications
The rapid proliferation of the Internet has been driving communication networks closer and closer to their limits, while available bandwidth is disappearing due to an ever-increasing network load. Over the past decade, optical fiber communication technology has increased per fiber data rate from 10 Tb/s to exceeding 10 Pb/s. The major explosion came after the maturity of coherent detection and advanced digital signal processing (DSP). DSP has played a critical role in accommodating channel impairments mitigation, enabling advanced modulation formats for spectral efficiency transmission and realizing flexible bandwidth. This book aims to explore novel, advanced DSP techniques to enable multi-Tb/s/channel optical transmission to address pressing bandwidth and power-efficiency demands. It provides state-of-the-art advances and future perspectives of DSP as well
Accelerated neuromorphic cybernetics
Accelerated mixed-signal neuromorphic hardware refers to electronic systems that emulate electrophysiological aspects of biological nervous systems in analog voltages and currents in an accelerated manner. While the functional spectrum of these systems already includes many observed neuronal capabilities, such as learning or classification, some areas remain largely unexplored. In particular, this concerns cybernetic scenarios in which nervous systems engage in closed interaction with their bodies and environments. Since the control of behavior and movement in animals is both the purpose and the cause of the development of nervous systems, such processes are, however, of essential importance in nature. Besides the design of neuromorphic circuit- and system components, the main focus of this work is therefore the construction and analysis of accelerated neuromorphic agents that are integrated into cybernetic chains of action. These agents are, on the one hand, an accelerated mechanical robot, on the other hand, an accelerated virtual insect. In both cases, the sensory organs and actuators of their artificial bodies are derived from the neurophysiology of the biological prototypes and are reproduced as faithfully as possible. In addition, each of the two biomimetic organisms is subjected to evolutionary optimization, which illustrates the advantages of accelerated neuromorphic nervous systems through significant time savings
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