DATA COMPRESSION USING EFFICIENT DICTIONARY SELECTION METHOD

With the increase in silicon densities, it is becoming feasible for compression systems to be implemented in chip. A system with distributed memory architecture is based on having data compression and decompression engines working independently on different data at the same time. This data is stored in memory distributed to each processor. The objective of the project is to design a lossless data compression system which operates in high-speed to achieve high compression rate. By using the architecture of compressors, the data compression rates are significantly improved. Also inherent scalability of architecture is possible. The main parts of the system are the data compressors and the control blocks providing control signals for the Data compressors, allowing appropriate control of the routing of data into and from the system. Each Data compressor can process four bytes of data into and from a block of data in every clock cycle. The data entering the system needs to be clocked in at a rate of 4 bytes in every clock cycle. This is to ensure that adequate data is present for all compressors to process rather than being in an idle state

Mathematical Model Validation of a Center of Gravity Measuring Platform Using Experimental Tests and FEA

This thesis sets out to derive an analytical model for a center of gravity (CG) measuring platform and examines its validity through experimental testing and Finite Element Modeling. The method uses a two-stage platform tilting process to first locate the planar CG coordinates and then find the third CG coordinate normal to the platform. An uncertainty model of the measuring platform was also developed, both CG and uncertainty models were implemented in the form of a MATLAB code. A load cell sizing task was also added to the code to assist the Integration Engineers at Jet Propulsion Laboratory in selecting load cells to design their own version of the CG Platform. The constructed CG Platform for this project used an array of six strain gauges, four C2A-06-062LT-120 Tee Rosettes and two C2A-06-031WW-120 Stacked Rosettes. They were bonded onto the legs of three truss shaped bipods. Results from the Platform Tilting Tests could not be used to validate the CG model as the measured CG and weight values found from the experimental tests contained a considerable amount of error. The errors in the Platform Tilting Tests are believed to stem from the initial errors observed during the bipod rod and strain gauge calibration tests. As an alternative, an FE model of the CG measuring platform was created as another means of validation. The math model of the CG measuring platform was successfully validated by showing that there was less than a 0.01% different between the bipod loads predicted from the MATLAB code and the FE model. Using the FEM generated loads as inputs into the CG code to calculate a CG matched the initial point mass or CG created in the FE model within a 0.01% difference. To validate the CG model even further, another test should be performed using a CG Platform prototype instrumented with load cells to generate new experimental data and compare them with the results from the FE model

Automated Debugging Methodology for FPGA-based Systems

Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

Bitmask-Based Code Compression for Embedded Systems

Embedded systems are constrained by the available memory. Code compression techniques address this issue by reducing the code size of application programs. It is a major challenge to develop an efficient code compression technique that can generate substantial reduction in code size without affecting the overall system performance. We present a novel code compression technique using bitmasks that significantly improves the compression efficiency without introducing any decompression penalty. This article makes three important contributions: i) it develops an efficient bitmask selection technique that can create a large set of matching patterns; ii) it develops an efficient dictionary selection technique based on bitmasks; and iii) it proposes a dictionary-based code compression algorithm using the bitmask and dictionary selection techniques that can significantly reduce the memory requirement. To demonstrate the usefulness of our approach we have performed code compression using applications from various domains and compiled for a wide variety of architectures. Our approach outperforms the existing dictionary-based techniques by an average of 20%, giving a compression ratio of 55 %- 65%