3,075 research outputs found

    Numerical methods for the determination of the properties and critical behaviour of percolation and the Ising model

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    For this thesis, numerical methods have been developed, based on Monte Carlo methods, which allow for investigating percolation and the Ising model with high precision. Emphasis is on methods to use modern parallel computers with high efficiency. Two basic approaches for parallelization were chosen: replication and domain decomposition, in conjunction with suitable algorithms. For percolation, the Hoshen-Kopelman algorithm for cluster counting was adapted to different needs. For studying fluctuations of cluster numbers, its traditional version (i. e., which is already published in literature) was used with simple replication. For simulating huge lattices, the Hoshen-Kopelman algorithm was adapted to domain decomposition, by dividing the hyperplane of investigation into strips that were assigned to different processors. By using this way of domain decomposition, it is viable to simulate huge lattices (with world record sizes) even for dimensions d greater than 2 on massively-parallel computers with distributed memory and message passing. For studying properties of percolation in dependence of system size, the Hoshen-Kopelman algorithm was modified to work on changing domains, i. e., growing lattices. By using this method, it is possible to simulate a lattice of linear size Lmax and investigate lattices of size L less than Lmax for free. Here again, replication is a viable parallelization strategy. For the Ising model, the standard Monte Carlo method of importance sampling with Glauber kinetics and multi-spin coding is adapted to parallel computers by domain decomposition of the lattice into strips. Using this parallelization method, it is possible to use massively-parallel computers with distributed memory and message passing in order to study huge lattices (again world record sizes) over many Monte Carlo steps, in order to investigate the dynamical critical behaviour in two dimensions

    Pseudorandomness for Regular Branching Programs via Fourier Analysis

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    We present an explicit pseudorandom generator for oblivious, read-once, permutation branching programs of constant width that can read their input bits in any order. The seed length is O(log2n)O(\log^2 n), where nn is the length of the branching program. The previous best seed length known for this model was n1/2+o(1)n^{1/2+o(1)}, which follows as a special case of a generator due to Impagliazzo, Meka, and Zuckerman (FOCS 2012) (which gives a seed length of s1/2+o(1)s^{1/2+o(1)} for arbitrary branching programs of size ss). Our techniques also give seed length n1/2+o(1)n^{1/2+o(1)} for general oblivious, read-once branching programs of width 2no(1)2^{n^{o(1)}}, which is incomparable to the results of Impagliazzo et al.Our pseudorandom generator is similar to the one used by Gopalan et al. (FOCS 2012) for read-once CNFs, but the analysis is quite different; ours is based on Fourier analysis of branching programs. In particular, we show that an oblivious, read-once, regular branching program of width ww has Fourier mass at most (2w2)k(2w^2)^k at level kk, independent of the length of the program.Comment: RANDOM 201

    A practical guide to computer simulations

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    Here practical aspects of conducting research via computer simulations are discussed. The following issues are addressed: software engineering, object-oriented software development, programming style, macros, make files, scripts, libraries, random numbers, testing, debugging, data plotting, curve fitting, finite-size scaling, information retrieval, and preparing presentations. Because of the limited space, usually only short introductions to the specific areas are given and references to more extensive literature are cited. All examples of code are in C/C++.Comment: 69 pages, with permission of Wiley-VCH, see http://www.wiley-vch.de (some screenshots with poor quality due to arXiv size restrictions) A comprehensively extended version will appear in spring 2009 as book at Word-Scientific, see http://www.worldscibooks.com/physics/6988.htm

    Quiescent current testing of CMOS data converters

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    Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

    The use of primitives in the calculation of radiative view factors

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    Compilations of radiative view factors (often in closed analytical form) are readily available in the open literature for commonly encountered geometries. For more complex three-dimensional (3D) scenarios, however, the effort required to solve the requisite multi-dimensional integrations needed to estimate a required view factor can be daunting to say the least. In such cases, a combination of finite element methods (where the geometry in question is sub-divided into a large number of uniform, often triangular, elements) and Monte Carlo Ray Tracing (MC-RT) has been developed, although frequently the software implementation is suitable only for a limited set of geometrical scenarios. Driven initially by a need to calculate the radiative heat transfer occurring within an operational fibre-drawing furnace, this research set out to examine options whereby MC-RT could be used to cost-effectively calculate any generic 3D radiative view factor using current vectorisation technologies

    Discrete-time integrated circuits for chaotic communication

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    This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using switched-capacitor techniques and designed in a 0.8 /spl mu/m CMOS technology are presented to validate the suitability of these systems for information encryption
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