Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field

A Sub-500 mu W Interface Electronics for Bionic Ears

This paper presents an ultra-low power current-mode circuit for a bionic ear interface. Piezoelectric (PZT) sensors at the system input transduce sound vibrations into multi-channel electrical signals, which are then processed by the proposed circuit to stimulate the auditory nerves consistently with the input amplitude level. The sensor outputs are first amplified and range-compressed through ultra-low power logarithmic amplifiers (LAs) into AC current waveforms, which are then rectified through custom current-mode circuits. The envelopes of the rectified signals are extracted, and are selectively sampled as reference for the stimulation current generator, armed with a 7-bit user-programmed DAC to enable patient fitting (calibration). Adjusted biphasic stimulation current is delivered to the nerves according to continuous inter-leaved sampling (CIS) stimulation strategy through a switch matrix. Each current pulse is optimized to have an exponentially decaying shape, which leads to reduced supply voltage, and hence similar to 20% lower stimulator power dissipation. The circuit has been designed and fabricated in 180nm high-voltage CMOS technology with up to 60 dB measured input dynamic range, and up to 1 mA average stimulation current. The 8-channel interface has been validated to be fully functional with 472 mu W power dissipation, which is the lowest value in the literature to date, when stimulated by a mimicked speech signal

Wireless integrated circuit for 100-channel charge-balanced neural stimulation

Journal ArticleThe authors present the design of an integrated circuit for wireless neural stimulation, along with benchtop and in-vivo experimental results. The chip has the ability to drive 100 individual stimulation electrodes with constant-current pulses of varying amplitude, duration, interphasic delay, and repetition rate. The stimulation is performed by using a biphasic (cathodic and anodic) current source, injecting and retracting charge from the nervous system. Wireless communication and power are delivered over a 2.765-MHz inductive link. Only three off-chip components are needed to operate the stimulator: a 10-nF capacitor to aid in power-supply regulation, a small capacitor (100 pF) for tuning the coil to resonance, and a coil for power and command reception. The chip was fabricated in a commercially available 0.6- m 2P3M BiCMOS process. The chip was able to activate motor fibers to produce muscle twitches via a Utah Slanted Electrode Array implanted in cat sciatic nerve, and to activate sensory fibers to recruit evoked potentials in somatosensory cortex

Low power circuits and systems for wireless neural stimulation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-161).Electrical stimulation of tissues is an increasingly valuable tool for treating a variety of disorders, with applications including cardiac pacemakers, cochlear implants, visual prostheses, deep brain stimulators, spinal cord stimulators, and muscle stimulators. Brain implants for paralysis treatments are increasingly providing sensory feedback via neural stimulation. Within the field of neuroscience, the perturbation of neuronal circuits wirelessly in untethered, freely-behaving animals is of particular importance. In implantable systems, power consumption is often the limiting factor in determining battery or power coil size, cost, and level of tissue heating, with stimulation circuitry typically dominating the power budget of the entire implant. Thus, there is strong motivation to improve the energy efficiency of implantable electrical stimulators. In this thesis, I present two examples of low-power tissue stimulators. The first type is a wireless, low-power neural stimulation system for use in freely behaving animals. The system consists of an external transmitter and a miniature, implantable wireless receiver-and-stimulator utilizing a custom integrated chip built in a standard 0.5 ptm CMOS process. Low power design permits 12 days of continuous experimentation from a 5 mAh battery, extended by an automatic sleep mode that reduces standby power consumption by 2.5x. To test this device, bipolar stimulating electrodes were implanted into the songbird motor nucleus HVC of zebra finches. Single-neuron recordings revealed that wireless stimulation of HVC led to a strong increase of spiking activity in its downstream target, the robust nucleus of the arcopallium (RA). When this device was used to deliver biphasic pulses of current randomly during singing, singing activity was prematurely terminated in all birds tested. The second stimulator I present is a novel, energy-efficient electrode stimulator with feedback current regulation. This stimulator uses inductive storage and recycling of energy based on a dynamic power supply to drive an electrode in an adiabatic fashion such that energy consumption is minimized. Since there are no explicit current sources or current limiters, wasteful energy dissipation across such elements is naturally avoided. The stimulator also utilizes a shunt current-sensor to monitor and regulate the current through the electrode via feedback, thus enabling flexible and safe stimulation. The dynamic power supply allows efficient transfer of energy both to and from the electrode, and is based on a DC-DC converter topology that is used in a bidirectional fashion. In an exemplary electrode implementation, I show how the stimulator combines the efficiency of voltage control and the safety and accuracy of current control in a single low-power integrated-circuit built in a standard 0.35 pm CMOS process. I also perform a theoretical analysis of the energy efficiency that is in accord with experimental measurements. In its current proof-of-concept implementation, this stimulator achieves a 2x-3x reduction in energy consumption as compared to a conventional current-source-based stimulator operating from a fixed power supply.by Scott Kenneth Arfin.Ph.D

Ultra-low-power circuits and systems for wearable and implantable medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 219-231).Advances in circuits, sensors, and energy storage elements have opened up many new possibilities in the health industry. In the area of wearable devices, the miniaturization of electronics has spurred the rapid development of wearable vital signs, activity, and fitness monitors. Maximizing the time between battery recharge places stringent requirements on power consumption by the device. For implantable devices, the situation is exacerbated by the fact that energy storage capacity is limited by volume constraints, and frequent battery replacement via surgery is undesirable. In this case, the design of energy-efficient circuits and systems becomes even more crucial. This thesis explores the design of energy-efficient circuits and systems for two medical applications. The first half of the thesis focuses on the design and implementation of an ultra-low-power, mixed-signal front-end for a wearable ECG monitor in a 0.18pm CMOS process. A mixed-signal architecture together with analog circuit optimizations enable ultra-low-voltage operation at 0.6V which provides power savings through voltage scaling, and ensures compatibility with state-of-the-art DSPs. The fully-integrated front-end consumes just 2.9[mu]W, which is two orders of magnitude lower than commercially available parts. The second half of this thesis focuses on ultra-low-power system design and energy-efficient neural stimulation for a proof-of-concept fully-implantable cochlear implant. First, implantable acoustic sensing is demonstrated by sensing the motion of a human cadaveric middle ear with a piezoelectric sensor. Second, alternate energy-efficient electrical stimulation waveforms are investigated to reduce neural stimulation power when compared to the conventional rectangular waveform. The energy-optimal waveform is analyzed using a computational nerve fiber model, and validated with in-vivo ECAP recordings in the auditory nerve of two cats and with psychophysical tests in two human cochlear implant users. Preliminary human subject testing shows that charge and energy savings of 20-30% and 15-35% respectively are possible with alternative waveforms. A system-on-chip comprising the sensor interface, reconfigurable sound processor, and arbitrary-waveform neural stimulator is implemented in a 0.18[mu]m high-voltage CMOS process to demonstrate the feasibility of this system. The sensor interface and sound processor consume just 12[mu]W of power, representing just 2% of the overall system power which is dominated by stimulation. As a result, the energy savings from using alternative stimulation waveforms transfer directly to the system.by Marcus Yip.Ph.D

Enhancing selectivity of minimally invasive peripheral nerve interfaces using combined stimulation and high frequency block: from design to application

The discovery of the excitable property of nerves was a fundamental step forward in our knowledge of the nervous system and our ability to interact with it. As the injection of charge into tissue can drive its artificial activation, devices have been conceived that can serve healthcare by substituting the input or output of the peripheral nervous system when damage or disease has rendered it inaccessible or its action pathological. Applications are far-ranging and transformational as can be attested by the success of neuroprosthetics such as the cochlear implant. However, the body’s immune response to invasive implants have prevented the use of more selective interfaces, leading to therapy side-effects and off-target activation. The inherent tradeoff between the selectivity and invasiveness of neural interfaces, and the consequences thereof, is still a defining problem for the field. More recently, continued research into how nervous tissue responds to stimulation has led to the discovery of High Frequency Alternating Current (HFAC) block as a stimulation method with inhibitory effects for nerve conduction. While leveraging the structure of the peripheral nervous system, this neuromodulation technique could be a key component in efforts to improve the selectivity-invasiveness tradeoff and provide more effective neuroprosthetic therapy while retaining the safety and reliability of minimally invasive neural interfaces. This thesis describes work investigating the use of HFAC block to improve the selectivity of peripheral nerve interfaces, towards applications such as bladder control or vagus nerve stimulation where selective peripheral nerve interfaces cannot be used, and yet there is an unmet need for more selectivity from stimulation-based therapy. An overview of the underlying neuroanatomy and electrophysiology of the peripheral nervous system combined with a review of existing electrode interfaces and electrochemistry will serve to inform the problem space. Original contributions are the design of a custom multi-channel stimulator able to combine conventional and high frequency stimulation, establishing a suitable experimental platform for ex-vivo electrophysiology of the rat sciatic nerve model for HFAC block, and exploratory experiments to determine the feasibility of using HFAC block in combination with conventional stimulation to enhance the selectivity of minimally-invasive peripheral nerve interfaces.Open Acces

A Wireless, High-Voltage Compliant, and Energy-Efficient Visual Intracortical Microstimulator

RÉSUMÉ L’objectif général de ce projet de recherche est la conception, la mise en oeuvre et la validation d’une interface sans fil intracorticale implantable en technologie CMOS avancée pour aider les personnes ayant une déficience visuelle. Les défis majeurs de cette recherche sont de répondre à la conformité à haute tension nécessaire à travers l’interface d’électrode-tissu (IET), augmenter la flexibilité dans la microstimulation et la surveillance multicanale, minimiser le budget de puissance pour un dispositif biomédical implantable, réduire la taille de l’implant et améliorer le taux de transmission sans fil des données. Par conséquent, nous présentons dans cette thèse un système de microstimulation intracorticale multi-puce basée sur une nouvelle architecture pour la transmission des données sans fil et le transfert de l’énergie se servant de couplages inductifs et capacitifs. Une première puce, un générateur de stimuli (SG) éconergétique, et une autre qui est un amplificateur de haute impédance se connectant au réseau de microélectrodes de l’étage de sortie. Les 4 canaux de générateurs de stimuli produisent des impulsions rectangulaires, demi-sinus (DS), plateau-sinus (PS) et autres types d’impulsions de courant à haut rendement énergétique. Le SG comporte un contrôleur de faible puissance, des convertisseurs numérique-analogiques (DAC) opérant en mode courant, générateurs multi-forme d’ondes et miroirs de courants alimentés sous 1.2 et 3.3V se servant pour l’interface entre les deux technologies utilisées. Le courant de stimulation du SG varie entre 2.32 et 220μA pour chaque canal. La deuxième puce (pilote de microélectrodes (MED)), une interface entre le SG et de l’arrangement de microélectrodes (MEA), fournit quatre niveaux différents de courant avec la valeur maximale de 400μA par entrée et 100μA par canal de sortie simultanément pour 8 à 16 sites de stimulation à travers les microélectrodes, connectés soit en configuration bipolaire ou monopolaire. Cette étage de sortie est hautement configurable et capable de délivrer une tension élevée pour satisfaire les conditions de l’interface à travers l’impédance de IET par rapport aux systèmes précédemment rapportés. Les valeurs nominales de plus grandes tensions d’alimentation sont de ±10V. La sortie de tension mesurée est conformément 10V/phase (anodique ou cathodique) pour les tensions d’alimentation spécifiées. L’incrémentation de tensions d’alimentation à ±13V permet de produire un courant de stimulation de 220μA par canal de sortie permettant d’élever la tension de sortie jusqu’au 20V par phase. Cet étage de sortie regroupe un commutateur haute tension pour interfacer une matrice des miroirs de courant (3.3V /20V), un registre à décalage de 32-bits à entrée sérielle, sortie parallèle, et un circuit dédié pour bloquer des états interdits.----------ABSTRACT The general objective of this research project is the design, implementation and validation of an implantable wireless intracortical interface in advanced CMOS technology to aid the visually impaired people. The major challenges in this research are to meet the required highvoltage compliance across electrode-tissue interface (ETI), increase lexibility in multichannel microstimulation and monitoring, minimize power budget for an implantable biomedical device, reduce the implant size, and enhance the data rate in wireless transmission. Therefore, we present in this thesis a multi-chip intracortical microstimulation system based on a novel architecture for wireless data and power transmission comprising inductive and capacitive couplings. The first chip is an energy-efficient stimuli generator (SG) and the second one is a highimpedance microelectrode array driver output-stage. The 4-channel stimuli-generator produces rectangular, half-sine (HS), plateau-sine (PS), and other types of energy-efficient current pulse. The SG is featured with low-power controller, current mode source- and sinkdigital- to-analog converters (DACs), multi-waveform generators, and 1.2V/3.3V interface current mirrors. The stimulation current per channel of the SG ranges from 2.32 to 220μA per channel. The second chip (microelectrode driver (MED)), an interface between the SG and the microelectrode array (MEA), supplies four different current levels with the maximum value of 400μA per input and 100μA per output channel. These currents can be delivered simultaneously to 8 to 16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. This output stage is highly-configurable and able to deliver higher compliance voltage across ETI impedance compared to previously reported designs. The nominal values of largest supply voltages are ±10V. The measured output compliance voltage is 10V/phase (anodic or cathodic) for the specified supply voltages. Increment of supply voltages to ±13V allows 220μA stimulation current per output channel enhancing the output compliance voltage up to 20V per phase. This output-stage is featured with a high-voltage switch-matrix, 3.3V/20V current mirrors, an on-chip 32-bit serial-in parallel-out shift register, and the forbidden state logic building blocks. The SG and MED chips have been designed and fabricated in IBM 0.13μm CMOS and Teledyne DALSA 0.8μm 5V/20V CMOS/DMOS technologies with silicon areas occupied by them 1.75 x 1.75mm2 and 4 x 4mm2 respectively. The measured DC power budgets consumed by low-and mid-voltage microchips are 2.56 and 2.1mW consecutively