End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Characterising Solder Materials from Random Vibration Response of their Interconnects in BGA Packaging

Solder interconnection in electronic packaging is the weakest link, thus driving the reliability of electronic modules and systems. Improving interconnection integrity in safety-critical applications is vital in enhancing application reliability. This investigation qualifies the random vibration response of five essential solder compositions in ball grid array (BGA) solder joints used in safety-critical applications. The solder compositions are eutectic Sn63Pb37 and SnAgCu (SAC) 305, 387, 396, and 405. Computer-aided engineering (CAE) employing ANSYS FEA and SolidWorks software is implemented in this investigation. The solder Sn63Pb37 deformed least at 0.43 µm, followed by SAC396 at 0.58 µm, while SAC405 deformed highest at 0.88 µm. Further analysis demonstrates that possession of higher elastic modulus and mass density culminates in lower solder joint deformation. Stress is concentrated at the periphery of the solder joints in contact with the printed circuit board (PCB). The SAC396 solder accumulates the lowest stress of 14.1 MPa, followed by SAC405 at 17.9 MPa, while eutectic Sn63Pb37 accrues the highest at 34.6 MPa. Similarly, strain concentration is found at the interface between the solder joint and copper pad on PCB. SAC405 acquires the lowest elastic strain magnitude of 0.0011 mm/mm, while SAC305 records the highest strain of 0.002 mm/mm. These results demonstrate that SAC405 solder has maximum and SAC387 solder has minimum fatigue lives

Properties of Mixing SAC Solder Alloys with Bismuth-containing Solder Alloys for a Low Reflow Temperature Process

The subject of extensive research has been the establishing of lower temperature soldering of electronic assemblies that are similar to the once common yet still preferred eutectic Tin-Lead (SnPb) soldering manufacturing processes that are below 217˚C. This research opportunity will contribute data on mixed solder alloy assemblies that can be formed at lower process temperatures. There are many environmental and economic benefits of avoiding the current reliability concerns of assembling electronics at the standard high temperatures which peak at 230˚C 260˚C. To reduce this temperature the use of Bismuth containing solder pastes are mixing with the standard high temperature SAC solders for electronic assemblies. The materials evaluated are the (in weight percentages) 96.5Tin/3Silver/.5Copper (Sn/Ag/Cu) solder ball mixed with each solder paste, the eutectic 58Bismuth/42Tin (58Bi/42Sn), 57Bi/42Sn /1Ag and a propriety alloy that has a lower Bismuth content along with various micro alloys, 40-58Bi/Sn/X (X representing proprietary micro alloys or doping). In the assembly portion of this research the solder alloys were exposed to three different peak temperatures 180˚C, 195˚C, 205˚C. Another reflow profile attribute of focus was times above 138˚C the melting point of the eutectic Sn58Bi alloy. The ball and paste assembly portion of this research used the times above melting of 120sec and 240sec to represent process extremes and verify their significance on improving mixing level results. These times above melting did not consistently improve the mixing levels and therefore are not recommended or required during mixed low temperature solder assemblies. The results in this study suggest the recommended and optimum reflow profile to have a time above the melting point to be less than or equal to 90 seconds for mixed solder alloy assemblies in “low” (20mm a side) component is a SAC405 solder balled BGA with the dimensions of 42x28x0.8mm. With any large component the temperature gradient across the component is a risk factor and the results show that there are significantly differences of mixing from the center of the component to the edge due to an average 2.3 ˚C temperature difference during convection reflow. The average mixing % levels recorded for Tpeak= 180˚C for the solder pastes with a 58Bi = 47%, 57Bi = 47% and 40-58Bi = 44%. The average mixing % levels recorded for Tpeak= 195˚C for the solder pastes with a 58Bi = 69%, 57Bi = 77% and 40-58Bi = 57%. The conclusions found also match previous work identifying the reflow peak temperatures remain a significant factor on the mixing %. This work’s goal was to add to the knowledge of the electronics industry to better understanding the microstructure and mixing mechanisms of Bi/Sn/X-SAC solder joints for low temperature reflow assembly processes

MODELING RATE DEPENDENT DURABILITY OF LOW-Ag SAC INTERCONNECTS FOR AREA ARRAY PACKAGES UNDER TORSION LOADS

The thesis discusses modeling rate-dependent durability of solder interconnects under mechanical torsion loading for surface mount area array components. The study discusses an approach to incorporate strain-rate dependency in durability estimation for solder interconnects. The components under study are two configurations of BGAs (ball grid array) assembled with select lead-free solders. A torsion test setup is used to apply displacement controlled loads on the test board. Accelerated test load profile is experimentally determined. Torsion test is carried out for all the components under investigation to failure. Strain-rate dependent (Johnson-Cook model) and strain-rate independent, elastic-plastic properties are used to model the solders in finite element simulation. Damage model from literature is used to estimate the durability for SAC305 solder to validate the approach. Test data is used to extract damage model constants for SAC105 solder and extract mechanical fatigue durability curve

Modelling of the reliability of flip chip lead-free solder joints at high-temperature excursions

At high-temperature operations of electronic control devices, Tin-Silver-Copper (SnAgCu) alloy solder joints used to assemble the component of the devices are functioning at homologous temperature above 0.8. In such ambient temperatures, solder alloys have limited mechanical strength and will be sensitive to strain rate. The sensitivity of solder properties to creep/visco-plastic deformation increases the rate of accumulation of plastic damage in the alloy and decreases the number of cycles to failure (Nf) of the joints. Most untimely rupture of solder joints in high-temperature electronics (HTE) system usually culminates in colossal loss of resources and lives. Typical incidences are reported in recent automotive and aircraft crashes as well as the collapse of oil-well logging equipment. To increase the mean time to failure (MTTF) of solder joints in HTE, an in-depth understanding and accurate prediction of the response of solder joints to thermally induced plastic strain damage is crucial. This study concerns the prediction of the reliability of lead-free solder joints in a flip chip (FC) model FC48D6.3C457 which is mounted on a substrate and the assembly subjected to high-temperature excursions. The research investigates the effect of the high-temperature operations on reliability of the joints. In addition, the investigation examines the impact of control factors (component stand-off height (CSH), inter-metallic compound (IMC) thickness, number of thermal cycle and solder volume) on Nf of the joints. A model developed in the course of this investigation was employed to create the assembly solder joints architecture. The development of the model and creation of the bump profile involve a combination of both analytical and construction methods. The assembled package on a printed circuit board (PCB) was subjected to accelerated temperature cycle (ATC) employing IEC standard 60749-25 in parts. The cycled temperature range is between -38 oC and 157 oC. Deformation behaviour of SnAgCu alloy solder in the joints is captured using Anand’s visco-plasticity model and the response of other materials in the assembly were simulated with appropriate model. The results demonstrate that the reliability of solder joints operating at elevated temperatures is dependent on CSH, thickness of IMC and solder volume. It also shows that incorporating the IMC layer in the geometric models significantly improves the level of accuracy of fatigue life prediction to ± 22.5% (from the ± 25% which is currently generally accepted). The findings also illustrate that the magnitude of the predicted damage and fatigue life are functions of the number of ATC employed. The extensive set of results from the modelling study has demonstrated the need for incorporating the IMC layer in the geometric model to ensure greater accuracy in the prediction of solder joint service life. The technique developed for incorporating the IMC layer will be of value to R&D engineers and scientists engaged in high-temperature applications in the automotive, aerospace and oil-well logging sectors. The results have been disseminated through peer reviewed journals and also presentations at international conferences

Modelling and simulation of paradigms for printed circuit board assembly to support the UK's competency in high reliability electronics

The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for ‘power-by-the-hour’ commercial aircraft operation business models. [Continues.

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk

Effect of temperature on the fracture behavior of lead-free solder joints

The objective of the present study is to examine the effect of temperature on the fracture behavior of Cu-SAC305-Cu joints. To this end, double cantilever beam (DCB) specimens, consisting of a thin layer of Sn96.5Ag3.0Cu0.5 (SAC305) solder sandwiched between two copper bars, fabricated under standard surface mount (SMT) processing conditions are fractured under various temperatures with a MTS machine equipped with an environment chamber. The load-displacement behavior corresponding to crack initiation and the subsequent toughening before ultimate failure and the displacements near crack tip are recorded and used to calculate the fracture energy release rates. The fracture surfaces and the crack path analyses are conducted with a scanning electron microscope to understand the effect of temperature on the mechanism of fracture. These results provide new information to manufacturers of microelectronics packages, which could be used to further improve package reliability

Analysis of Printed Circuit Boards strains using finite element analysis and digital image correlation

This paper investigates the use of digital image correlation (DIC) and finite element analysis for strain measurement on Printed Board Circuits (PCBs). Circuit boards (PCBs) are designed to mechanically support and electrically connect an electronic component assembly. Due to screw assemblies, the surface level differences on which the PCB is placed, the process of assembling the electronic components induces a certain state of stress and deformation in the PCB. The main components affected are microprocessors due to the way they are glued to PCBs with BGA - Ball grid arrays (BGA). Digital Image Correlation (DIC) is a full-field contactless optical method for measuring displacements and strain in experimental testing, based on the correlation of images taken during test. The experimental setup is realized with Dantec Q-400 system used for image capture and Istra 4D software for image correlations and data analyses. The maximum level of the obtained strain is compared with the allowable limit. Finite element analysis (FEA) is a numerical method of analysis for stresses and strain in structures of any given geometry