Precise linear signal generation with nonideal components and deterministic dynamic element matching

A dynamic element matching (DEM) approach to ADC testing is introduced. Two variants of this method are introduced and compared; a deterministic DEM method and a random DEM method. With both variants, a highly non-ideal DAC is used to generate an excitation for a DUT that has effective linearity that far exceeds that of the DAC. Simulation results show that both methods can be used for testing of ADCs. The deterministic DEM (DDEM) offers potential for a substantial reduction in the number of samples when compared with a random DEM approach with the same measurement accuracy. It is shown that the concept of usinf DEM for signal generation in a test environment finds applications well-beyond ADC testing. The DDEM approach offers potential for use in both production test and BIST environments

On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing

This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

On-the-fly computation method in field-programmable gate array for analog-to-digital converter linearity testing

© 2018 Published by ITB Journal Publisher. This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

Methodology for testing high-performance data converters using low-accuracy instruments

There has been explosive growth in the consumer electronics market during the last decade. As the IC industry is shifting from PC-centric to consumer electronics-centric, digital technologies are no longer solving all the problems. Electronic devices integrating mixed-signal, RF and other non-purely digital functions are becoming new challenges to the industry. When digital testing has been studied for long time, testing of analog and mixed-signal circuits is still in its development stage. Existing solutions have two major problems. First, high-performance mixed-signal test equipments are expensive and it is difficult to integrate their functions on chip. Second, it is challenging to improve the test capability of existing methods to keep up with the fast-evolving performance of mixed-signal products demanded on the market. The International Technology Roadmap for Semiconductors identified mixed-signal testing as one of the most daunting system-on-a-chip challenges;My works have been focused on developing new strategies for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Different from conventional methods that require test instruments to have better performance than the device under test, our algorithms allow the use of medium and low-accuracy instruments in testing. Therefore, we can provide practical and accurate test solutions for high-performance data converters. Meanwhile, the test cost is dramatically reduced because of the low price of such test instruments. These algorithms have the potential for built-in self-test and can be generalized to other mixed-signal circuitries. When incorporated with self-calibration, these algorithms can enable new design techniques for mixed-signal integrated circuits. Following contents are covered in the dissertation:;(1) A general stimulus error identification and removal (SEIR) algorithm that can test high-resolution ADCs using two low-linearity signals with a constant offset in between; (2) A center-symmetric interleaving (CSI) strategy for generating test signals to be used with the SEIR algorithm; (3) An architecture-based test algorithm for high-performance pipelined or cyclic ADCs using a single nonlinear stimulus; (4) Using Kalman Filter to improve the efficiency of ADC testing; and (5) A testing algorithm for high-speed high-resolution DACs using low-resolution ADCs with dithering

Deterministic dynamic element matching: an enabling technology for SoC built-in-self-test

The analog-to-digital converter (ADC) is a key building block of today\u27s high-volume systems-on-a-chip (SoCs). Built-in-self-test (BIST) is the most promising solution to testing deeply-embedded ADCs. Cost-effective stimulus source with on-chip integrability has been viewed as the bottleneck of ADC BIST, and consequentially the bottleneck of SoC BIST and BIST-based self-calibration. The deterministic dynamic element matching (DDEM) technique has been proposed as a solution to this problem;In this work, rigorous theoretical analysis is presented to show the performance of a DDEM digital-to-analog converter (DAC) as an ADC linearity test stimulus source. Guided by the insight obtained this analysis, a systematic approach for cost-effective DDEM DAC design is proposed. Two generations of DDEM DACs have been designed, fabricated, and measured. 12-bit equivalent linearity was achieved from the first DDEM DAC with 8-bit apparent resolution and less than 5-bit raw linearity after systematic error compensation. The achieved 12-bit linearity outperforms any on-chip stimulus source in literature. Based on the first design, a new DDEM DAC with 12-bit apparent resolution, 10-bit raw linearity, and 9-bit DDEM switching was designed with improved design technique. This DAC was fabricated in standard 0.5-pm CMOS technology with a core die area of 2 mm2. Clear ramp signals could be observed on an oscilloscope when the DDEM DAC was clocked at 100 MHz. Laboratory testing results confirmed that the new DDEM DAC achieved at least a 16-bit equivalent linearity; this was limited by the available instrumentation, which has 18-bit linearity. It outperforms any previously reported on-chip stimulus source in terms of ADC BIST performance by 5 bits. The robust performance, low cost, and short design cycle for on-chip implementation make DDEM an enabling technology for SoC BIST and self-calibration;Two new approaches based on DDEM are developed to further boost the die area efficiency, improving the basic DDEM approach. The first is termed segmented DDEM, and the second is dither-incorporated DDEM (DiDDEM). It has been shown through mathematical analysis and simulation that these can maintain the performance of the basic DDEM approach while greatly reducing the implementation cost

Accurate spectral testing without accurate instrumentation

Analog-to-digital converters (ADCs) are becoming increasingly common in many systems in integrated circuits. Spectral testing is widely used to test the dynamic linearity performance of ADCs and waveform generators. With improvements in the performance of ADCs, it is becoming an expensive and challenging task to perform spectral testing using standard methods because of the requirement that the test instrumentation environment must satisfy several stringent conditions. In order to address these challenges and to decrease the test cost, in this dissertation, four new algorithms are proposed to perform accurate spectral testing of ADCs by relaxing three conditions required for standard spectral testing methods. The first method developed is relaxing the requirements on precise control of coherent sampling and input signal amplitude. The efficiency and accuracy of this method is similar to the straightforward FFT, but it can simultaneously handle amplitude clipping and noncoherent sampling. By replacing a noncoherent and clipped fundamental with a coherent and unclipped one, correct spectral specifications can be obtained. Both simulation and measurement results validated the proposed method. The second algorithm can simultaneously perform the linearity test and the spectral test with only one-time data acquisition. Targeted for realizing the cotest of linearity and spectral performance under noncoherent sampling and amplitude clipping, a new accurate method for identifying the noncoherent and clipped fundamental is introduced. The residue after removing the identified fundamental from raw data is used to obtain the linearity and spectral characterizations. Simulation and measurement results against the standard test methods collaborate to validate the accuracy and robustness of the new solution. The third method proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying a simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics need not be known before the processing. The algorithm is robust enough that nonharmonic spurs do not affect the estimation result. Using the proposed algorithm, specifications of the ADC under test can be obtained without the jitter effect. Simulation results of ADCs with different resolutions show the functionality and accuracy of the method. The last method is developed to accurately estimate the SNR with sampling clock jitter. This method does not require a precise sampling clock and thus reduces the test cost. The ADC output sequence is separated into two segments. By analyzing the difference of the two segments, the RMS of jitter and the noise power are estimated, and then the SNR is obtained. Simulation and measurement results against the standard test methods collaborate to validate the accuracy and robustness of the new solution

Accurate spectral test algorithms with relaxed instrumentation requirements

Spectral testing is widely used to test the dynamic linearity performance of Analog-to-Digital Converters (ADC) and waveform generators. Dynamic specifications for ADCs are very important in high speed applications such as digital communications, ultrasound imaging and instrumentation. With improvements in the performance of ADCs, it is becoming an expensive and challenging task to perform spectral testing using standard methods due to the requirement that the test instrumentation environment must satisfy several stringent conditions. In order to address these challenges and to decrease the test cost, in this dissertation, three new algorithms are proposed to perform accurate spectral testing of ADCs by relaxing three necessary conditions required for standard spectral testing methods. The testing is done using uniformly sampled points. The first method introduces a new fundamental identification and replacement (FIRE) method, which eliminates the requirement of coherent sampling when using the DFT for testing the spectral response of an ADC. The robustness and accuracy of the proposed FIRE method is verified using simulation and measurement results obtained with non-coherently sampled data. The second method, namely, the Fundamental Estimation, Removal and Residue Interpolation (FERARI) method, is proposed to eliminate the requirement of precise control over amplitude and frequency of the input signal to the ADC. This method can be used when the ADC output is both non-coherently sampled and clipped. Simulation and measurement results using the FERARI method with non-coherently sampled and clipped outputs of the ADC are used to validate this approach. A third spectral test method is proposed that simultaneously relaxes the conditions of using a spectrally pure input source and coherent sampling. Using this method, the spectral characteristics of a high resolution ADC can be accurately tested using a non-coherently sampled output obtained with a sinusoidal input signal that has significant and unknown levels of nonlinear distortion. Simulation results are presented that show the accuracy and robustness of the proposed method. Finally, the issue of metastability in comparators and Successive Approximation Register (SAR) ADCs is analyzed. The analysis of probability of metastability in SAR ADCs with and without using metastable detection circuits is provided. Using this analysis, it is shown that as the frequency of sampling clock increases, using a metastable detection circuit decreases the probability of metastability in SAR ADC

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation