Adaptive code division multiple access protocol for wireless network-on-chip architectures

Massive levels of integration following Moore\u27s Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects

Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

The massive levels of integration following Moore\u27s Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC\u27s is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC\u27s to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator

System Level Analysis And Design For Wireless Inter-Chip Interconnection Communication Systems By Applying Advanced Wireless Communication Technologies

As the dramatic development of high speed integrated circuits has progressed, the 60 GHz silicon technology has been introduced to enable much faster computer systems and their corresponding applications. However, when signals are propagating at 60 GHz or higher frequencies on a PCB (Printed Circuit Board), the crosstalk among signal buses and devices, trace losses, and introduced parasitic capacitance and inductance between high density traces, become significant and may be severe enough such that the inter-chip communications will not be able to meet computer system signal specifications. High speed circuit signal integrity researchers in both electronic industries and academia have explored various methodologies to resolve these high frequency issues. Moreover, Intel is introducing Ultra Path Interconnect (UPI) for multi-core server systems, which demands more than 2.44 Tbps data rate between two CPUs, and 1.5 Tbps data rate for PCIe channel operation. Recently, the concept of the wireless inter/intra-chip interconnection (WIIC) technology was introduced [19, 23] for solving high frequency signal integrity issues. Here this dissertation mainly focuses on the inter-chip case while still using the WIIC designation for generality. Various WIIC technologies have been presented in the literature, which have focused on the investigations on Ultra Wide-Band (UWB), propagation channels, modulations, antennas, and power controls and interference. However, not much research has focused on a system level design, which includes the lowest two layers of the communication protocol in a WIIC system, namely, the physical, and data link layers. Also, the previously published literature has rarely reached the data rate at 100 Gbps or higher, and none of the prior research has obtained a spectrum utilization ratio of 4 bit/Hz or greater. In addition, currently existing research has not fully taken advantage of advanced and matured wireless communication technologies such as Orthogonal Frequency Division Multiplexing (OFDM), high order modulation, and Multiple-Input/Multiple-Output (MIMO) systems for increasing data rates and improving reliability, although the use of UWB [29], conventional FDMA or TDMA [39], and binary modulations including Binary Phase Shift Keying (BPSK) [22], On-Off Keying (OOK) [31], and Amplitude Shift Keying (ASK) [35] have been studied in previous research. In this dissertation, a complete WIIC system and a representative WIIC channel model have been developed by taking full advantages of advanced wireless communication techniques. First, this research has analyzed the potential of higher-order modulation, error correction, OFDM, and channel coding to the WIIC setting. Although MIMO, interleaving and scrambling are also analyzed but not included in the current version of the proposed WIIC system, they could be featured in hypothetically ideal future research to determine their potential benefits. Second, the performance of a proposed WIIC system has been analyzed in order to reach 100 Gbps data rate. Third, a 60 GHz WIIC channel based on metamaterial Electronic Band Gap (EBG) absorbers has been designed and analyzed using the numerical electromagnetics solver HFSS® and this EBG is integrated into the representative WIIC channel. Moreover, the impulse response of the WIIC channel is numerically extracted and is used for the system validation and testing. Furthermore, the system has been simulated with the WIIC channel and the wired PCB channel. It has been found that, the Bit Error Rate (BER) performance of the proposed WIIC channel is close to that of an AWGN channel with FEC, and much better than the AWGN channel without FEC, which means that the designed WIIC system and channel work properly within the frequency band centered at 60 GHz, while the wired PCB channel is almost cut off at 15 GHz or higher for the cases investigated. With only five or six layers on a PCB board, the WIIC system is able to provide 384 Gbps data rate theoretically with 12 GHz bandwidth, while the wired PCB counterpart needs more than 20 layers in order to avoid severe SI problems and to properly layout the Tbps channels. The current version of the WIIC system is able to provide 24 Gbps data rate with the bandwidth of 12 GHz using OFDM and QPSK

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

A General Framework for Analyzing, Characterizing, and Implementing Spectrally Modulated, Spectrally Encoded Signals

Fourth generation (4G) communications will support many capabilities while providing universal, high speed access. One potential enabler for these capabilities is software defined radio (SDR). When controlled by cognitive radio (CR) principles, the required waveform diversity is achieved via a synergistic union called CR-based SDR. Research is rapidly progressing in SDR hardware and software venues, but current CR-based SDR research lacks the theoretical foundation and analytic framework to permit efficient implementation. This limitation is addressed here by introducing a general framework for analyzing, characterizing, and implementing spectrally modulated, spectrally encoded (SMSE) signals within CR-based SDR architectures. Given orthogonal frequency division multiplexing (OFDM) is a 4G candidate signal, OFDM-based signals are collectively classified as SMSE since modulation and encoding are spectrally applied. The proposed framework provides analytic commonality and unification of SMSE signals. Applicability is first shown for candidate 4G signals, and resultant analytic expressions agree with published results. Implementability is then demonstrated in multiple coexistence scenarios via modeling and simulation to reinforce practical utility

Robust and Traffic Aware Medium Access Control Mechanisms for Energy-Efficient mm-Wave Wireless Network-on-Chip Architectures

To cater to the performance/watt needs, processors with multiple processing cores on the same chip have become the de-facto design choice. In such multicore systems, Network-on-Chip (NoC) serves as a communication infrastructure for data transfer among the cores on the chip. However, conventional metallic interconnect based NoCs are constrained by their long multi-hop latencies and high power consumption, limiting the performance gain in these systems. Among, different alternatives, due to the CMOS compatibility and energy-efficiency, low-latency wireless interconnect operating in the millimeter wave (mm-wave) band is nearer term solution to this multi-hop communication problem. This has led to the recent exploration of millimeter-wave (mm-wave) wireless technologies in wireless NoC architectures (WiNoC). To realize the mm-wave wireless interconnect in a WiNoC, a wireless interface (WI) equipped with on-chip antenna and transceiver circuit operating at 60GHz frequency range is integrated to the ports of some NoC switches. The WIs are also equipped with a medium access control (MAC) mechanism that ensures a collision free and energy-efficient communication among the WIs located at different parts on the chip. However, due to shrinking feature size and complex integration in CMOS technology, high-density chips like multicore systems are prone to manufacturing defects and dynamic faults during chip operation. Such failures can result in permanently broken wireless links or cause the MAC to malfunction in a WiNoC. Consequently, the energy-efficient communication through the wireless medium will be compromised. Furthermore, the energy efficiency in the wireless channel access is also dependent on the traffic pattern of the applications running on the multicore systems. Due to the bursty and self-similar nature of the NoC traffic patterns, the traffic demand of the WIs can vary both spatially and temporally. Ineffective management of such traffic variation of the WIs, limits the performance and energy benefits of the novel mm-wave interconnect technology. Hence, to utilize the full potential of the novel mm-wave interconnect technology in WiNoCs, design of a simple, fair, robust, and efficient MAC is of paramount importance. The main goal of this dissertation is to propose the design principles for robust and traffic-aware MAC mechanisms to provide high bandwidth, low latency, and energy-efficient data communication in mm-wave WiNoCs. The proposed solution has two parts. In the first part, we propose the cross-layer design methodology of robust WiNoC architecture that can minimize the effect of permanent failure of the wireless links and recover from transient failures caused by single event upsets (SEU). Then, in the second part, we present a traffic-aware MAC mechanism that can adjust the transmission slots of the WIs based on the traffic demand of the WIs. The proposed MAC is also robust against the failure of the wireless access mechanism. Finally, as future research directions, this idea of traffic awareness is extended throughout the whole NoC by enabling adaptiveness in both wired and wireless interconnection fabric

Ultra Wideband

Ultra wideband (UWB) has advanced and merged as a technology, and many more people are aware of the potential for this exciting technology. The current UWB field is changing rapidly with new techniques and ideas where several issues are involved in developing the systems. Among UWB system design, the UWB RF transceiver and UWB antenna are the key components. Recently, a considerable amount of researches has been devoted to the development of the UWB RF transceiver and antenna for its enabling high data transmission rates and low power consumption. Our book attempts to present current and emerging trends in-research and development of UWB systems as well as future expectations

Performance analysis of ultra wide band indoor channel

This thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering, 2008.Cataloged from PDF version of thesis report.Includes bibliographical references (page 41).Research on wireless communication system has been pursued for many years, but there is a renewed interest in ultra-wideband (UWB) technology for communication within short range, because of its huge bandwidth and low radiated power level. This emerging technology provides extremely high data rate in short ranges but in more secured approach. In order to build systems that realize all the potential of UWB, it is first required to understand UWB propagation and the channel properties arise from the propagation. In this research, the properties of UWB channel for indoor industrial environment was evaluated. A few indoor channel models have been studied so far for different environments but not for indoor industrial environment and various data rates are obtained according to wireless channel environments. Therefore, an accurate channel model is required to determine the maximum achievable data rate. In this thesis, we have proposed a channel model for indoor industrial environment considering the scattering coefficient along with the other multipath gain coefficient. This thesis addresses scattering effect while modeling UWB channel. Here, the performance of UWB channel model is analyzed following the parameters, such as power delay profile and the temporal dispersion properties which are also investigated in this paper.Kazi Afrina YasmeenA. K. M. WahiduzzamanMD. Ahamed ImtiazB. Computer Science and Engineerin

UWB Radio Wireless Communication System Design for Railway Tunnels

Railway is an economical and comfortable mode of transportation for long distances. Safety, reliability and good quality of service are the main concern of railway industries which are maintained by railway management and communication system. There are several existing management systems like CCCS, ATCS, PTC and many more. With increasing population, demand for railway services also increases. To full fill these demands railway infrastructure has been developing continuously. By implementing latest technologies for railway communication we can make railway transportation safer, efficient, and more accessible. Ultra wideband radio communication system is amongst those very latest and rapidly growing technologies. This research work focuses on the study of UWB radio based wireless communication system for railway tunnels, whose main task is to maintain an uninterrupted data transmission between train driver to wayside controller