Automatic Number Plate Recognition on FPGA

Automatic Number Plate Recognition (ANPR) systems have become one of the most important components in the current Intelligent Transportation Systems (ITS). In this paper, a FPGA implementation of a complete ANPR system which consists of Number Plate Localisation (NPL), Character Segmentation (CS), and Optical Character Recognition (OCR) is presented. The Mentor Graphics RC240 FPGA development board was used for the implementation, where only 80% of the available on-chip slices of a Virtex-4 LX60 FPGA have been used. The whole system runs with a maximum frequency of 57.6 MHz and is capable of processing one image in 11ms with a successful recognition rate of 93%

Real-Time Vision System for License Plate Detection and Recognition on FPGA

Rapid development of the Field Programmable Gate Array (FPGA) offers an alternative way to provide acceleration for computationally intensive tasks such as digital signal and image processing. Its ability to perform parallel processing shows the potential in implementing a high speed vision system. Out of numerous applications of computer vision, this paper focuses on the hardware implementation of one that is commercially known as Automatic Number Plate Recognition (ANPR).Morphological operations and Optical Character Recognition (OCR) algorithms have been implemented on a Xilinx Zynq-7000 All-Programmable SoC to realize the functions of an ANPR system. Test results have shown that the designed and implemented processing pipeline that consumed 63 % of the logic resources is capable of delivering the results with relatively low error rate. Most importantly, the computation time satisfies the real-time requirement for many ANPR applications

PCA-RECT: An Energy-efficient Object Detection Approach for Event Cameras

We present the first purely event-based, energy-efficient approach for object detection and categorization using an event camera. Compared to traditional frame-based cameras, choosing event cameras results in high temporal resolution (order of microseconds), low power consumption (few hundred mW) and wide dynamic range (120 dB) as attractive properties. However, event-based object recognition systems are far behind their frame-based counterparts in terms of accuracy. To this end, this paper presents an event-based feature extraction method devised by accumulating local activity across the image frame and then applying principal component analysis (PCA) to the normalized neighborhood region. Subsequently, we propose a backtracking-free k-d tree mechanism for efficient feature matching by taking advantage of the low-dimensionality of the feature representation. Additionally, the proposed k-d tree mechanism allows for feature selection to obtain a lower-dimensional dictionary representation when hardware resources are limited to implement dimensionality reduction. Consequently, the proposed system can be realized on a field-programmable gate array (FPGA) device leading to high performance over resource ratio. The proposed system is tested on real-world event-based datasets for object categorization, showing superior classification performance and relevance to state-of-the-art algorithms. Additionally, we verified the object detection method and real-time FPGA performance in lab settings under non-controlled illumination conditions with limited training data and ground truth annotations.Comment: Accepted in ACCV 2018 Workshops, to appea

Optical character recognition on heterogeneous SoC for HD automatic number plate recognition system

Automatic number plate recognition (ANPR) systems are becoming vital for safety and security purposes. Typical ANPR systems are based on three stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR). Recently, high definition (HD) cameras have been used to improve their recognition rates. In this paper, four algorithms are proposed for the OCR stage of a real-time HD ANPR system. The proposed algorithms are based on feature extraction (vector crossing, zoning, combined zoning, and vector crossing) and template matching techniques. All proposed algorithms have been implemented using MATLAB as a proof of concept and the best one has been selected for hardware implementation using a heterogeneous system on chip (SoC) platform. The selected platform is the Xilinx Zynq-7000 All Programmable SoC, which consists of an ARM processor and programmable logic. Obtained hardware implementation results have shown that the proposed system can recognize one character in 0.63 ms, with an accuracy of 99.5% while utilizing around 6% of the programmable logic resources. In addition, the use of the heterogenous SoC consumes 36 W which is equivalent to saving around 80% of the energy consumed by the PC used in this work, whereas it is smaller in size by 95%

Pay as You Go: A Generic Crypto Tolling Architecture

The imminent pervasive adoption of vehicular communication, based on dedicated short-range technology (ETSI ITS G5 or IEEE WAVE), 5G, or both, will foster a richer service ecosystem for vehicular applications. The appearance of new cryptography based solutions envisaging digital identity and currency exchange are set to stem new approaches for existing and future challenges. This paper presents a novel tolling architecture that harnesses the availability of 5G C-V2X connectivity for open road tolling using smartphones, IOTA as the digital currency and Hyperledger Indy for identity validation. An experimental feasibility analysis is used to validate the proposed architecture for secure, private and convenient electronic toll payment