Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits

This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology

Evaluación eléctrica y física de métodos de generación de redes lógicas para compuertas estáticas CMOS complementarias (SCCG)

Recientemente la evolución de la industria de la microelectrónica ha permitido el desarrollo de herramientas de diseño electrónico automático (EDA), las cuales tienen por objetivo optimizar el proceso de diseño de circuitos integrados (IC). Tradicionalmente en la creación de un IC se suele utilizar el enfoque de diseño de celdas estándar; no obstante, este tipo de flujo de diseño se encuentra limitado por la cantidad de compuertas lógicas que estén definidas en la librería utilizada. Es por ello que diversos estudios han realizado investigaciones respecto a la optimización de circuitos por Compuertas CMOS Estáticas Complementarias (SCCG). En la literatura podemos encontrar diversas estrategias de diseño de compuertas SCCG; sin embargo, la métrica que se usa para definir el mejor arreglo es la cantidad de transistores, la cual carece de otros análisis concernientes a los parámetros eléctricos y físicos. Es por ello que en este trabajo de tesis se plantea evaluarlas redes de transistores SCCG generadas por el framework SwitchCraft mediante un análisis eléctrico realizado con el software CADENCE y un análisis físico de los layouts generados por medio de la herramienta ASTRAN

Algorithms for Cell Layout

Cell layout is a critical step in the design process of computer chips. A cell is a logic function or storage element implemented in CMOS technology by transistors connected with wires. As each cell is used many times on a chip, improvements of a single cell layout can have a large effect on the overall chip performance. In the past years increasing difficulty to manufacture small feature sizes has lead to growing complexity of design rules. Producing cell layouts which are compliant with design rules and at the same time optimized w.r.t. layout size has become a difficult task for human experts. In this thesis we present BonnCell, a cell layout generator which is able to fully automatically produce design rule compliant layouts. It is able to guarantee area minimality of its layouts for small and medium sized cells. For large cells it uses a heuristic which produces layouts with a significant area reduction compared to those created manually. The routing problem is based on the Vertex Disjoint Steiner Tree Packing Problem with a large number of additional design rules. In Chapter 4 we present the routing algorithm which is based on a mixed integer programming (MIP) formulation that guarantees compliance with all design rules. The algorithm can also handle instances in which only part of the transistors are placed to check whether this partial placement can be extended to a routable placement of all transistors. Chapter 5 contains the transistor placement algorithm. Based on a branch and bound approach, it places transistors in turn and achieves efficiency by pruning parts of the search tree which do not contain optimum solutions. One major contribution of this thesis is that BonnCell only outputs routable placements. Simply checking the routability for each full placement in the search tree is too slow in practice, therefore several speedup strategies are applied. Some cells are too large to be solved by a single call of the placement algorithm. In Chapter 7 we describe how these cells are split up into smaller subcells which are placed and routed individually and subsequently merged into a placement and routing of the original cell. Two approaches for dividing the original cell into subcells are presented, one based on estimating the subcell area and the other based on solving the Min Cut Linear Arrangement Problem. BonnCell has enabled our cooperation partner IBM to drastically improve their cell design and layout process. In particular, a team of human experts needed several weeks to find a layout for their largest cell, consisting of 128 transistors. BonnCell processed this cell without manual intervention in 3 days and its layout uses 15% less area than the layout found by the human experts

NASA Tech Briefs, December 1999

Topics include: Imaging/Videos/Cameras; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Books and Reports

Large space structures and systems in the space station era: A bibliography with indexes

Bibliographies and abstracts are listed for 1372 reports, articles, and other documents introduced into the NASA scientific and technical information system between January 1, 1990 and June 30, 1990. Its purpose is to provide helpful information to the researcher, manager, and designer in technology development and mission design according to system, interactive analysis and design, structural and thermal analysis and design, structural concepts and control systems, electronics, advanced materials, assembly concepts, propulsion, and solar power satellite systems

NASA Tech Briefs, May 2000

Topics include: Sensors: Test and Measurement; Computer-Aided Design and Engineering; Electronic Components and Circuits; Electronic Systems; Composites and Plastics; Materials; Computer Programs; Mechanics

Climate Change and Air Pollution Effects on Forest Ecosystems

Both climate change and air pollution have large negative impacts on physiological processes and functions at the individual tree level and on whole forest ecosystems. The objective of climate change and air quality monitoring is to make decisions, based on scientific knowledge, regarding how to best manage and improve the current state of the environment. Our ability to take urgent measures to combat climate change and its impact on forest ecosystems and conserve forest biodiversity depends upon our knowledge of the latest scientific results on the status of forest ecosystems. Unfortunately, there are a lot of gaps in our knowledge of the detection and monitoring of their effects on forest ecosystems. This book presents relevant results from scientific research in the fields of climate change, air pollution, forest conservation, protection and monitoring that can contribute to a better science–policy interaction and to the elaboration of specific strategies, in accordance with the areas of forest sciences from IUFRO RG 8.04.00 - Impacts of air pollution and climate change on forest ecosystems