NSSDC Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications, volume 1

Papers and viewgraphs from the conference are presented. This conference served as a broad forum for the discussion of a number of important issues in the field of mass storage systems. Topics include magnetic disk and tape technologies, optical disks and tape, software storage and file management systems, and experiences with the use of a large, distributed storage system. The technical presentations describe, among other things, integrated mass storage systems that are expected to be available commercially. Also included is a series of presentations from Federal Government organizations and research institutions covering their mass storage requirements for the 1990's

Scalable Reliable SD Erlang Design

This technical report presents the design of Scalable Distributed (SD) Erlang: a set of language-level changes that aims to enable Distributed Erlang to scale for server applications on commodity hardware with at most 100,000 cores. We cover a number of aspects, specifically anticipated architecture, anticipated failures, scalable data structures, and scalable computation. Other two components that guided us in the design of SD Erlang are design principles and typical Erlang applications. The design principles summarise the type of modifications we aim to allow Erlang scalability. Erlang exemplars help us to identify the main Erlang scalability issues and hypothetically validate the SD Erlang design

Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility

The purpose of this investigation is to demonstrate value for Auto Defect Classification (ADC) for patterned wafer inspection systems within a high volume manufacturing fabrication in the Process Limited Yield (PLY) defect area. Process excursions in all functional Unit Process (UP) areas, examples are of etch, litho, diffusion, are monitored by PLY. Troubleshooting of process excursions using added defect density count with a small percentage (random or largest 50 examples) of and inline Scanning Electron Microscope (SEM) data classification review does not give a clear indication of the full wafer data. Statistical Process Control (SPC) trigging on total counts or defect density is not as powerful as making excursion decisions on classified data from ADC (Fisher, 2002). The ADC data gives classification of the entire wafer rather than a smaller sample making signature analysis to be an additional troubleshooting tool. The inline ADC data does not have near the resolution of the SEM but can be used to help make important decisions to what is occurring in the manufacturing line. The interest is to gain a full understanding of the current capabilities and limitation of ADC and to apply the learning to enable faster reaction and visibility into process and tool excursions within a high volume manufacturing fabrication. The Technical Learning Vehicle (TLV), high running product layer at the leading design rule, there were approximately 10,000 wafers a week with 1000 wafer die (chips) per wafer. A sustained improvement in yield of 1% across the entire manufacturing line would equate to almost 1 million dollars a month of saving. With the ability to tightly control multiple etch process tools, the resulting yield improvement was 3% across 15% of the line. With the baseline yield improvement along with ability to react quickly to process excursions, the combined improvement resulted in excessive of 5 million dollar a year of reoccurring savings

Strategies for Optimising DRAM Repair

Dynamic Random Access Memories (DRAM) are large complex devices, prone to defects during manufacture. Yield is improved by the provision of redundant structures used to repair these defects. This redundancy is often implemented by the provision of excess memory capacity and programmable address logic allowing the replacement of faulty cells within the memory array. As the memory capacity of DRAM devices has increased, so has the complexity of their redundant structures, introducing increasingly complex restrictions and interdependencies upon the use of this redundant capacity. Currently redundancy analysis algorithms solving the problem of optimally allocating this redundant capacity must be manually customised for each new device. Compromises made to reduce the complexity, and human error, reduce the efficacy of these algorithms. This thesis develops a methodology for automating the customisation of these redundancy analysis algorithms. Included are: a modelling language describing the redundant structures (including the restrictions and interdependencies placed upon their use), algorithms manipulating this model to generate redundancy analysis algorithms, and methods for translating those algorithms into executable code. Finally these concepts are used to develop a prototype software tool capable of generating redundancy analysis algorithms customised for a specified device

Proceedings of the NSSDC Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications

The proceedings of the National Space Science Data Center Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications held July 23 through 25, 1991 at the NASA/Goddard Space Flight Center are presented. The program includes a keynote address, invited technical papers, and selected technical presentations to provide a broad forum for the discussion of a number of important issues in the field of mass storage systems. Topics include magnetic disk and tape technologies, optical disk and tape, software storage and file management systems, and experiences with the use of a large, distributed storage system. The technical presentations describe integrated mass storage systems that are expected to be available commercially. Also included is a series of presentations from Federal Government organizations and research institutions covering their mass storage requirements for the 1990's

Memory built-in self-repair and correction for improving yield: a review

Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories