Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Deep Learning Algorithm for Advanced Level-3 Inverse-Modeling of Silicon-Carbide Power MOSFET Devices

Inverse modelling with deep learning algorithms involves training deep architecture to predict device's parameters from its static behaviour. Inverse device modelling is suitable to reconstruct drifted physical parameters of devices temporally degraded or to retrieve physical configuration. There are many variables that can influence the performance of an inverse modelling method. In this work the authors propose a deep learning method trained for retrieving physical parameters of Level-3 model of Power Silicon-Carbide MOSFET (SiC Power MOS). The SiC devices are used in applications where classical silicon devices failed due to high-temperature or high switching capability. The key application of SiC power devices is in the automotive field (i.e. in the field of electrical vehicles). Due to physiological degradation or high-stressing environment, SiC Power MOS shows a significant drift of physical parameters which can be monitored by using inverse modelling. The aim of this work is to provide a possible deep learning-based solution for retrieving physical parameters of the SiC Power MOSFET. Preliminary results based on the retrieving of channel length of the device are reported. Channel length of power MOSFET is a key parameter involved in the static and dynamic behaviour of the device. The experimental results reported in this work confirmed the effectiveness of a multi-layer perceptron designed to retrieve this parameter.Comment: 13 pages, 8 figures, to be published on Journal of Physics: Conference Serie

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

SIMPLIS efficiency model for a synchronous multiphase buck converter

In this master’s thesis, an efficiency model was developed for the synchronous multiphase buck converters of the TPS6594x-Q1 integrated circuit using SIMPLIS simulator. The model includes internal losses occurring in power stage transistors, power stage drivers and bondwires. Modeled external losses include printed circuit board resistance and inductance, inductor direct and alternating current characteristics as well as capacitor nonidealities. Internal loss modeling was mostly based on Cadence simulations. Power stage transistors especially were thoroughly modeled. The capacitances of the power stage transistors were extracted by integrating gate and drain currents during the transistor on and off transitions. Charging of the parasitic capacitances followed the theory in turn-off and turn-on transitions and therefore the capacitance extraction was fairly simple. Nonlinearities of the parasitic capacitors were modeled in SIMPLIS with multiple linear approximations. Transistor gate drivers were very rough approximations of the real drivers but good enough for the simulation model. Drivers were modeled to match the gate currents simulated in Cadence, which were then combined the accurate switching transistor models in order to accurately model the switching characteristics. External loss models were based on measurements and simulations. Printed circuit board losses were based on Ansys simulations in which the printed circuit board inductances and resistances were solved from the geometry of the printed circuit board. Inductors were modeled to match the datasheet impedance and resistance graphs and the model was verified against the measurements done in the laboratory. An automated measurement testbench was done for the inductor measurements using LabVIEW and the results were parsed using Matlab. A ladder topology with resistances and inductances was used in the final inductor model to model the frequency characteristics of the inductor. The effect of direct current on inductance was also investigated but the inductance reduction did not have any significant impact on efficiency. Other external components such as capacitors also cause some external losses and they were modeled based on the capacitor datasheets. The simulation model was compared against single- and two-phase efficiency measurements with multiple different input and output voltages which were chosen to match the most common use cases. Efficiency curves were drawn for each configuration using the implemented simulation model and over 300 different comparison points were compared in total. A post processing script that was launched after a simulation completes had to be written with the programming language SIMPLIS supports to draw the efficiency graph from the simulated data. Using the script allowed to run the efficiency simulation without any additional licenses other than the SIMPLIS license. The final model achieved an average error of under 1 % between all the measured and simulated efficiency curves. The most accurate results were obtained with lower switching frequency and larger inductance. Apart from accuracy, the simulator had to be practical and therefore the simulation time had to be considered. Simulation time was attempted to be kept at minimum by simplifying the schematic in as many ways as possible without losing accuracy. For example, reducing the point of the linear approximations in the power stage transistors from 79 points to 17 points saved nearly 50 seconds in single-phase simulations without significant changes in simulation accuracy

Parameter extraction of Extended Floating Gate Field Effect Transistors (EGFETs): Estimating the threshold voltage, series resistance, and mobility degradation from I-V measurements

Extended Floating Gate Field Effect Transistors (EGFETs) are CMOS-compatible floating gate devices capable of detecting charges on their sensing area by the relative shifts in current-voltage (I-V) characteristics. The I-V shifts are generally computed by measuring the EGFET parameters in the strong inversion region of operation. This could lead to errors in estimating the device sensitivity because the simple I-V model ignores the mobility degradation and series resistance effects in EGFETs. Our goal is to model these parasitic effects and present methods to extract the key device parameters. We derive an analytical I-V model for EGFETs in the linear region of transistor operation, accounting for both the mobility degradation and series resistance effects. Based on the analytical model, three methods are presented to estimate the key parameters, namely the threshold voltage, series resistance, surface roughness parameter, low-field mobility, and effective mobility from the I-V characteristics, gate transconductance, and drain conductance. The peak transconductance method is used as a benchmark for comparing the extracted threshold voltages. Silicon-based EGFET devices are fabricated, and their I-V characteristics are measured with deionized water and three polyelectrolytes. From the I-V data, the parameter extraction methods are used to compute the values of the key parameters, and the suitability of each method is discussed. The gate transconductance methods show good agreement between the values for the key parameters, while the drain transconductance method gives lower values of the key parameters. There is scope to improve the presented methods by incorporating the effects of substrate bias and asymmetric series resistance for new extended-gate device architectures, including solution-based organic field-effect transistors.Comment: 19 pages, 8 figures, preprin

Compact Modeling of SiC Insulated Gate Bipolar Transistors

This thesis presents a unified (n-channel and p-channel) silicon/silicon carbide Insulated Gate Bipolar Transistor (IGBT) compact model in both MAST and Verilog-A formats. Initially, the existing MAST model mobility equations were updated using recently referenced silicon carbide (SiC) data. The updated MAST model was then verified for each device tested. Specifically, the updated MAST model was verified for the following IGBT devices and operation temperatures: n-channel silicon at 25 ˚C and at 125 ˚C; n-channel SiC at 25 ˚C and at 175 ˚C; and p-channel SiC at 150 ˚C and at 250 ˚C. Verification was performed through capacitance, DC output characteristics, and turn-off transient simulations. The validated MAST model was then translated into the Verilog-A language, and the Verilog-A model results were validated against the updated MAST model

Modeling of SIC P-Channel Insulated Gate Bipolar Transistors (IGBTS)

A new physics-based IGBT compact model has been developed for circuit simulation of silicon (Si) or silicon carbide (SiC) devices. The model accurately predicts the steady-state output, transfer and switching characteristics of the IGBT under a variety of different conditions. This is the first IGBT model to predict the behavior of p-channel SiC IGBTs. Previous work on IGBT models has focused on Si n-channel IGBTs [1-3]. This unified model is not limited to SiC p-channel IGBTs; the user has the option to select between Si or SiC, and n-channel or p-channel, making it the first IGBT model that captures the physics of all of these device and material types. The model also accounts for temperature effects, often referred to as temperature scaling, that have been experimentally validated up to 300 ºC for SiC. Validation of n-channel and p-channel devices was accomplished by fitting the steady-state characteristics and inductive load switching transient waveforms. 15-kV p-channel IGBTs supplied by Cree were among those used for validation [6]. The fitting was achieved using Certify, a software tool developed at the University of Arkansas. A parameter extraction recipe for the model was developed for simple parameter extraction using data that are readily available from datasheets. That fitting tool is available to the public through the National Center for Reliable Electric Power Transmission website (ncrept.eleg.uark.edu). The model and parameter extraction recipe will also be made available to the public through NCREP

Modeling and Validation of 4H-SiC Low Voltage MOSFETs for Integrated Circuit Design

Silicon Carbide is a promising wide bandgap material and gradually becoming the first choice of semiconductor for high density and high efficiency power electronics in medium voltage range (500-1500V). SiC has also excellent thermal conductivity and the devices fabricated with the material can operate at high temperature (~ 400 ⁰C). Thus, a power electronic system built with SiC devices requires less cooling requirement and saves board space and cost. The high temperature applications of SiC material can also be extended to space exploration, oil and gas rigging, aerospace and geothermal energy systems for data acquisition, sensing and instrumentation and power conditioning and conversion. But the high temperature capability of SiC can only be utilized when the integrated circuits can be designed in SiC technology and high fidelity compact models of the semiconductor devices are a priori for reliable and high yielding integrated circuit design. The objective of this work is to develop industry standard compact models for SiC NMOS and PMOS devices. A widely used compact model used in silicon industry called BSIM3V3 is adopted as a foundation to build the model for SiC MOSFET. The models optimized with the built-in HSPICE BSIM3V3.3 were used for circuit design in one tape-out but BSIM3V3 was found to be inadequate to model all of the characteristics of SiC MOSFET due to the presence of interface trapped charge. In the second tape-out, the models for SiC NMOS and PMOS were optimized based on the built-in HSPICE BSIM4V6.5 and a number of functioning circuits which have been published in reputed journal and conference were designed based on the models. Although BSIM4 is an enhanced version of BSIM3V3, it also could not model a few deviant SiC MOSFET characteristics such as body effect, soft saturation etc. The new model developed for SiC NMOS and PMOS based on BSIM4V7.0 is called BSIM4SIC and can model the entire range of device characteristics of the devices. The BSIM4SIC models are validated with a wide range of measured data and verified using the models in the simulation of numerous circuits such as op-amp, comparator, linear regulator, reference and ADC/DAC