Составление расписания для графов синхронных потоков данных

Розглянуто задачу складання розкладу для алгоритму, який заданий графом синхронних потоків даних (ГСПД). Запропоновано метод складання періодичного розкладу ГСПД з періодом L тактів, оснований на перетворенні його у просторовий ГСПД, вершини якого мають координати місця та моменту виконання відповідних операторів алгоритму. На координати просторового ГСПД накладено обмеження: оператори, які виконуються в одному процесорному елементі, не повинні мати однакові такти свого виконання, які взято за модулем L. Завдяки цьому ГСПД відображається у спеціалізований обчислювач, який виконує алгоритм у конвеєрному режимі з оптимізованою завантаженністю ресурсів. Показано алгоритм пошуку субоптимального розкладу на основі просторового ГСПД.The scheduling problem for the synchronous dataflow graph (SDF) is considered. A method of the SDF scheduling is proposed which is based on transforming SDF into spatial SDF. The circular schedule has the period of L cycles. Each spatial SDF node has the coordinates of space and time of an event, where and when the respective algorithm steps were performed. A set of restrictions, which the SDF nodes have, helps to derive the circular schedule with the optimum load balancing. So, the nodes, which are mapped into a single resource, must not have the same clock cycles modulo L, and the number of such nodes has to approach L. The resulting schedule is implemented in the pipelined datapath. The algorithm for computing the suboptimal schedule is proposed based on the spatial SDF.Рассмотрена задача составления расписания для алгоритма, заданного графом синхронных потоков данных (ГСПД). Предложен метод составления расписания ГСПД с периодом L тактов, основанный на преобразовании его в пространственный ГСПД, вершины которого имеют координаты места и момента выполнения соответствующих операторов алгоритма. На координаты пространственного ГСПД наложены ограничения: операторы, исполняемые в дном процессорном элементе, не должны иметь одинаковые такты своего исполнения, взятые по модулю L. Благодаря этому ГСПД отображается в специализированный вычислитель, исполняющий алгоритм в конвейерном режиме с оптимизированной загруженностью ресурсов. Показан алгоритм поиска субоптимального расписания на основе пространственного ГСПД

The interconnection problem

AbstractIn this paper the problem of interconnecting circuit modules in microprocessor and digital system design is studied. The data transfers are expressed by m sets Ti of directed edges between modules. An interconnecting schema, which is given by an assignment of the data transfers to buses, consists of the links between modules and buses. At first we show, that the problem of finding an assignment with minimum number of links is NP-complete. After that we prove that the problem of using a given interconnection schema is NP-complete, too

VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library

A statistical-based scheduling algorithm in automated data path synthesis

In this paper, we propose a new heuristic scheduling algorithm based on the statistical analysis of the cumulative frequency distribution of operations among control steps. It has a tendency of escaping from local minima and therefore reaching a globally optimal solution. The presented algorithm considers the real world constraints such as chained operations, multicycle operations, and pipelined data paths. The result of the experiment shows that it gives optimal solutions, even though it is greedy in nature

Microarchitecture optimization for timing and layout

In recent years the drive to produce more complex integrated circuits while spending less design time has driven the demand for design automation tools. The search for design automation methods has resulted in the design of numerous behavioral synthesis and logic synthesis tools. This report describes a system that fills the gap between traditional behavioral synthesis and logic synthesis tools. Techniques are introduced for improving the microarchitecture structure and using feedback from lower-level optimization tools to guide design optimizations while attempting to meet user specified area and time constraints. These techniques include the capability for mixing layout styles such as custom layout for random-logic components and bit-slicing for regularly structured components. In this manner the entire design, control logic and datapath, can be optimized at the same time. Further, this paper presents a new methodology for microarchitecture-level optimization that greatly reduces the amount of technology-specific knowledge necessary to perform the optimizations

Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages

科研費報告書収録論文(課題番号:17300009/研究代表者:亀山充隆/システムインテグレーション理論に基づく高安全知能自動車用VLSIの最適設計

Enumerating All Maximal Clique-Partitions of an Undirected Graph

We address the problem of enumerating all maximal clique-partitions of an undirected graph and present an algorithm based on the observation that every maximal clique-partition can be produced from the maximal clique-cover of the graph by assigning the vertices shared among maximal cliques, to belong to only one clique. This simple algorithm has the following drawbacks: (1) the search space is very large; (2) it finds some clique-partitions which are not maximal; and (3) some clique-partitions are found more than once. We propose two criteria to avoid these drawbacks. The outcome is an algorithm that explores a much smaller search space and guarantees that every maximal clique-partition is computed only once. The algorithm can be used in problems such as anti-unification with proximity relations or in resource allocation tasks when one looks for several alternative ways to allocate resources.Comment: In Proceedings FROM 2023, arXiv:2309.1295