Autarkies for DQCNF

Autarkies for dependency-quantified boolean CNFs are introduced, with basic theory and algorithms

On the Complexity of k-DQBF

Recently Dependency Quantified Boolean Formula (DQBF) has attracted a lot of attention in the SAT community. Intuitively, a DQBF is a natural extension of quantified boolean formula where for each existential variable, one can specify the set of universal variables it depends on. It has been observed that a DQBF with k existential variables - henceforth denoted by k-DQBF - is essentially a k-CNF formula in succinct representation. However, beside this and the fact that the satisfiability problem is NEXP-complete, not much is known about DQBF. In this paper we take a closer look at k-DQBF and show that a number of well known classical results on k-SAT can indeed be lifted to k-DQBF, which shows a strong resemblance between k-SAT and k-DQBF. More precisely, we show the following. a) The satisfiability problem for 2- and 3-DQBF is PSPACE- and NEXP-complete, respectively. b) There is a parsimonious polynomial time reduction from arbitrary DQBF to 3-DQBF. c) Many polynomial time projections from SAT to languages in NP can be lifted to polynomial time reductions from the satisfiability of DQBF to languages in NEXP. d) Languages in the class NSPACE[s(n)] can be reduced to the satisfiability of 2-DQBF with O(s(n)) universal variables. e) Languages in the class NTIME[t(n)] can be reduced to the satisfiability of 3-DQBF with O(log t(n)) universal variables. The first result parallels the well known classical results that 2-SAT and 3-SAT are NL- and NP-complete, respectively

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Efficient local search for Pseudo Boolean Optimization

Algorithms and the Foundations of Software technolog

Proceedings of Formal Methods in Computer-Aided Design, FMCAD 2019

Table of Contents: Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties / by Rohit Dureja, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman and Kristin Yvonne Rozier (p. 1) -- Input Elimination Transformations for Scalable Verification and Trace Reconstruction / by Raj Kumar Gajavelly, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman and Shiladitya Ghosh (p. 10) -- Chasing Minimal Inductive Validity Cores in Hardware Model Checking / by Ryan Berryhill and Andreas Veneris (p. 19) -- Verifying Large Multipliers by Combining SAT and Computer Algebra / by Daniela Kaufmann, Armin Biere and Manuel Kauers (p. 28) -- Unification-based Pointer Analysis without Oversharing / by Jakub Kuderski, Jorge A. Navas and Arie Gurfinkel (p. 37) -- Concurrent Chaining Hash Maps for Software Model Checking / by Freark I. van der Berg and Jaco van de Pol (p. 46) -- Proving Data Race Freedom in Task Parallel Programs with a Weaker Partial Order / by Benjamin Ogles, Peter Aldous and Eric Mercer (p. 55) -- BDD-Based Algorithms for Packet Classification / by Nina Narodytska, Leonid Ryzhyk, Igor Ganichev and Soner Sevinc (p. 64) -- TSNsched: Automated Schedule Generation for Time Sensitive Networking / by Aellison Cassimiro Teixeira Dos Santos, Ben Schneider and Vivek Nigam (p. 69) -- Verification and Synthesis of Symmetric Uni-Rings for Leads-To Properties / by Ali Ebnenasir (p. 78) -- Scalable Translation Validation of Unverified Legacy OS Code / by Amer Tahat, Sarang Joshi, Pronnoy Goswami and Binoy Ravindran (p. 87) -- Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity / by Faria Kalim, Karl Palmskog, Jayasi Mehar, Adithya Murali, Indranil Gupta and P. Madhusudan (p. 96) -- KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design / by Luca Piccolboni, Giuseppe Di Guglielmo and Luca Carloni (p. 105) -- Verification of Authenticated Firmware Loaders / by Sujit Kumar Muduli, Pramod Subramanyan and Sayak Ray (p. 110) -- Learning-Based Synthesis of Safety Controllers / by Daniel Neider and Oliver Markgraf (p. 120) -- Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems / by Meng Wu, Jingbo Wang, Jyotirmoy Deshmukh and Chao Wang (p. 129) -- Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications / by Gideon Geier, Philippe Heim, Felix Klein and Bernd Finkbeiner (p. 138) -- Synthesizing Reactive Systems Using a Robustness Specification / by Roderick Bloem, Hana Chockler, Masoud Ebrahimi and Ofer Strichman (p. 147) -- Property Directed Inference of Relational Invariants / by Dmitry Mordvinov and Grigory Fedyukovich (p. 152) -- Knowledge Compilation for Boolean Functional Synthesis / by S. Akshay, Jatin Arora, Supratik Chakraborty, Krishna S, Divya Raghunathan and Shetal Shah (p. 161) -- Verifying Relational Properties using Trace Logic / by Gilles Barthe, Renate Eilers, Pamina Georgiou, Bernhard Gleiss, Laura Kovacs and Matteo Maffei (p. 170) -- Autarkies for DQCNF / by Oliver Kullmann and Ankit Shukla (p. 179) -- Localizing Quantifiers for DQBF / by Aile Ge-Ernst, Christoph Scholl and Ralf Wimmer (p. 184) -- Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization / by Alexander Nadel (p. 193) -- GuidedSampler: Coverage-guided Sampling of SMT Solutions / by Rafael Dutra, Jonathan Bachrach and Koushik Sen (p. 203) -- Extending enumerative function synthesis via SMT-driven classification / by Haniel Barbosa, Andrew Reynolds, Daniel Larraz and Cesare Tinelli (p. 212) -- Proving Non-Termination via Loop Acceleration / by Florian Frohn and Jürgen Giesl (p. 221)Computer Science