Development of an Oxygen Saturation Monitoring System by Embedded Electronics

Measuring Oxygenation of blood (SaO2) plays a vital role in patient’s health monitoring. This is often measured by pulse oximeter, which is standard measure during anesthesia, asthma, operative and post-operative recoveries. Despite all, monitoring Oxygen level is necessary for infants with respiratory problems, old people, and pregnant women and in other critical situations. This paper discusses the process of calculating the level of oxygen in blood and heart-rate detection using a non-invasive photo plethysmography also called as pulsoximeter using the MSP430FG437 microcontroller (MCU). The probe uses infrared lights to measure and should be in physical contact with any peripheral points in our body. The percentage of oxygen in the body is worked by measuring the intensity from each frequency of light after it transmits through the body and then calculating the ratio between these two intensities

A LVDS Serial AER Link

Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows to analyse a LVDS Serial AER link. The interface allows up to 0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0

A performance analysis of the PASLIB version 2.1X SEND and RECV routines on the finite element machine

The Finite Element Machine is an experimental array processor designed to support research in parallel algorithms and architectures. This report presents a case study of communications using the SENDa and RECV system software routines on the Finite Element Machine, followed by a discussion of the effect of I/O performance on the efficiency of parallel algorithms

Design and implementation of a microcomputer-based user interface controller for bursted data communications satellite ground terminals

The NASA Lewis Research Center is developing a laboratory-based satellite communications test bed for evaluation of state-of-the-art communications hardware and systems. Most of the digital components of the ground terminals are being constructed in-house at NASA Lewis. One of the ground terminal subsystems, the user interface controller, controls the connection and disconnection of all users to the communication network. The role of the user interface controller in the ground terminal is described and the design and implementation of the microcomputer-based subsystem is discussed

Parallel software tools at Langley Research Center

This document gives a brief overview of parallel software tools available on the Intel iPSC/860 parallel computer at Langley Research Center. It is intended to provide a source of information that is somewhat more concise than vendor-supplied material on the purpose and use of various tools. Each of the chapters on tools is organized in a similar manner covering an overview of the functionality, access information, how to effectively use the tool, observations about the tool and how it compares to similar software, known problems or shortfalls with the software, and reference documentation. It is primarily intended for users of the iPSC/860 at Langley Research Center and is appropriate for both the experienced and novice user

EXTEND-L : an input language for extensible register transfer compilation

This report discusses the model and input language for EXTEND, a synthesis system that permits extensible register transfer synthesis. EXTEND-L fills the need for a language that bridges the gap between existing behavioral input descriptions, which are too abstract, and structural schematics, which cannot capture the high-level behavior. The report first discusses previous work in behavioral synthesis and summarizes the deficiencies of these behavioral specifications. The report then describes the proposed langauge in detail, and concludes with a few examples that show its utility

Neuromorphic Approach Sensitivity Cell Modeling and FPGA Implementation

Neuromorphic engineering takes inspiration from biology to solve engineering problems using the organizing principles of biological neural computation. This field has demonstrated success in sensor based applications (vision and audition) as well in cognition and actuators. This paper is focused on mimicking an interesting functionality of the retina that is computed by one type of Retinal Ganglion Cell (RGC). It is the early detection of approaching (expanding) dark objects. This paper presents the software and hardware logic FPGA implementation of this approach sensitivity cell. It can be used in later cognition layers as an attention mechanism. The input of this hardware modeled cell comes from an asynchronous spiking Dynamic Vision Sensor, which leads to an end-to-end event based processing system. The software model has been developed in Java, and computed with an average processing time per event of 370 ns on a NUC embedded computer. The output firing rate for an approaching object depends on the cell parameters that represent the needed number of input events to reach the firing threshold. For the hardware implementation on a Spartan6 FPGA, the processing time is reduced to 160 ns/event with the clock running at 50 MHz.Ministerio de Economía y Competitividad TEC2016-77785-PUnión Europea FP7-ICT-60095