Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Energy and area efficient techniques for data converters

Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research focuses on achieving this goal by enabling circuit techniques, architecture techniques and calibration methods. The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques. 1. A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs. 2. Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables asynchronous ADC architectures for energy efficient system. 3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques. Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply, the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V supply and achieves a figure of merit of 40 fJ/C-S. 4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace the function of flash ADC and the DAC references in a pipeline ADC. The simulated/ extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming approximately 8-9 mA from 1 V supply. 5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients for ADCs. A three-path ADC can restore the ADC performance independent of the input frequency and number of errors in a single path. 6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity

Ring amplification for switched capacitor circuits

A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification

Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit

Ultra Low Power Circuits for Internet of Things and Deep Learning Accelerator Design with In-Memory Computing

Collecting data from environment and converting gathered data into information is the key idea of Internet of Things (IoT). Miniaturized sensing devices enable the idea for many applications including health monitoring, industrial sensing, and so on. Sensing devices typically have small form factor and thus, low battery capacity, but at the same time, require long life time for continuous monitoring and least frequent battery replacement. This thesis introduces three analog circuit design techniques featuring ultra-low power consumption for such requirements: (1) An ultra-low power resistor-less current reference circuit, (2) A 110nW resistive frequency locked on-chip oscillator as a timing reference, (3) A resonant current-mode wireless power receiver and battery charger for implantable systems. Raw data can be efficiently transformed into useful information using deep learning. However deep learning requires tremendous amount of computation by its nature, and thus, an energy efficient deep learning hardware is highly demanded to fully utilize this algorithm in various applications. This thesis also presents a pulse-width based computation concept which utilizes in-memory computing of SRAM.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/144173/1/myungjun_1.pd

Trains, Games, and Complexity: 0/1/2-Player Motion Planning through Input/Output Gadgets

We analyze the computational complexity of motion planning through local "input/output" gadgets with separate entrances and exits, and a subset of allowed traversals from entrances to exits, each of which changes the state of the gadget and thereby the allowed traversals. We study such gadgets in the 0-, 1-, and 2-player settings, in particular extending past motion-planning-through-gadgets work to 0-player games for the first time, by considering "branchless" connections between gadgets that route every gadget's exit to a unique gadget's entrance. Our complexity results include containment in L, NL, P, NP, and PSPACE; as well as hardness for NL, P, NP, and PSPACE. We apply these results to show PSPACE-completeness for certain mechanics in Factorio, [the Sequence], and a restricted version of Trainyard, improving prior results. This work strengthens prior results on switching graphs and reachability switching games.Comment: 37 pages, 36 figure

Digital control for automating feed distribution in feedlots

An investigation was conducted to determine the feasibility of automatic controls to automate feed distribution in feedlots. The control approach was restricted to compatibility with conventional feeding equipment. Input control signals were taken to originate from commonly available mechanical and electronic sensors. The control system was implemented with standard digital logic components;The proposed digital control system is based on a railguided, self-propelled automatic vehicle capable of delivering feed sequentially to 255 pens located on both sides of a single feeding path. A manual, closed-loop control system consisting of the following functions was developed: (1) pen identification, (2) initialization control, (3) feeding mode, (4) exit from feeding mode, (5) re-entry into feeding mode, (6) end of feeding cycle, (7) ground drive and conveyor control, (8) interface and auto/manual mode, (9) monitoring of automated system and (10) data and failure display and alarm. The control system allows either automatic or manual operation of the feeding vehicle. Digital electronic circuits capable of implementing the desired control functions were designed;The feeding cycle is manually initiated and automatically terminated when feed has been delivered to all pens requiring feed. It can be partially programmed to enable feed delivery to sections of the feedlot. Two feed rations can be delivered. The feeding status of each pen is recorded. The pen feed rations are stored in reprogrammable memories;The operation of the automated feeding system is based on the automatic identification of the feedlot pens. The number assigned to a pen is coded, using binary pulse-code modulation. Frequency-shift keying is used to transmit the coded number. The received coded number is recovered by specialized communication circuits and then validated;The control system monitors the vehicle components and the major electronic circuits to detect failures, prevent damage and produce a safe operation. Furthermore, it incorporates safety sensors and logic circuitry to meet the basic safety requirements pertaining to automated vehicles;The proposed automated feed distribution system for feedlots is expected to: (1) reduce management requirements through automatic distribution of feed to cattle raised in pens, (2) increase efficiency of feeding operation by eliminating time losses associated with secondary feed transfer, (3) eliminate damage to feedbunks through positive guidance of the vehicle by rails, and (4) save energy by eliminating secondary feed transfer

A new modular multilevel converter for HVDC applications

In the coming years, due to an increasing shift towards electric mobility and further industrialisation, a rapid growth in the demand for electricity is expected. At the same time, this energy demand must be met in a clean and sustainable manner, to reduce climate change as well as to ensure security of supply. It is predicted that the High Voltage Direct Current (HVDC) transmission technology will play a key role in the future power systems which are expected to feature higher levels of interconnection and more renewable-based generation. HVDC transmission is preferred over AC transmission in applications such as power transmission over long distances and from offshore wind sources, and interconnection of asynchronous systems. The main elements of an HVDC system are the AC/DC converters that take up the majority of the initial set up cost, and therefore, there has been a huge focus lately on improving these converters in terms of functionality, cost and efficiency. Today, the state-of-the-art converter topology for Voltage Source Converters (VSC) based HVDC transmission is the Modular Multilevel Converter (MMC), which replaced the earlier two- and three-level VSC topologies. Recently, a new breed of VSC converters, known as the `hybrid VSCs' are introduced, that combine the aspects of two- and three-level VSCs with the modular multilevel structure of the MMC. In this work, a new hybrid VSC, the Switched Mid-Point Converter (SMPC), has been proposed. While maintaining the same efficiency as the MMC, the energy storage requirement of the SMPC is shown to be less than half of that of the MMC. The operating principle and the particular voltage waveshaping of the chainlinks of the submodules is investigated. For effective operation of the SMPC, suitable control strategies are proposed. The converter concept and the developed control schemes are verified both using computer simulations and a lab-scaled experimental prototype