Power-efficient memory bus encoding using stride-based stream reconstruction

With the rapid increase in the complexity of chips and the popularity of portable devices, the performance demand is not any more the only important constraint in the embedded system. In stead, energy consumption has become one of the main design issues for contemporary embedded systems, especially for I/O interface due to the high capacitance of bus transition. In this paper, we propose a bus encoding scheme, which may reduce transitions by reconstructing active address streams with variable cached strides. The key idea is to obtain the variable strides for dierent sets of active addressing streams such that the decoder reconstructs these interlaced streams with these strides. Instead of sending the full address, the encoder may only send partial ad- dress or stride by using either one-hot or binary-inversion encoding. To exploit the locality and dynamically adjust the value of stride of active address streams, we partially compare the previous addresses of existing streams with the current address. Hence, the data transmitted on the bus can be minimally encoded. Experiments with several MediaBench benchmarks show that the scheme can achieve an average of 60% reduction in bus switching activity.Facultad de Informátic

Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression

In this paper, we propose an implementation of a data encoder to reduce the switched capacitance on a system bus. Our technique focuses on transferring raw video data for multiple reference frames between off-and on-chip memories in an MPEG-4 AVC/H.264 encoder. This technique is based on entropy coding to minimize bus transition. Existing techniques exploit the correlation between neighboring pixels. In our proposed technique, we exploit pixel correlation between two consecutive frames. Our method achieves a 58% power saving compared to an unencoded bus when transferring pixels on a 32-b off-chip bus with a 15-pF capacitance per wire

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Energy macro-model for on chip interconnection buses

This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be able to evaluate the energy metrics for the bus under a certain traffic and information coding.Peer Reviewe

Methodologies for Designing Power-Aware Smart Card Systems

Smart cards are some of the smallest computing platforms in use today. They have limited resources, but a huge number of functional requirements. The requirement for multi-application cards increases the demand for high performance and security even more, whereas the limits given by size and energy consumption remain constant. We describe new methodologies for designing and implementing entire systems with regard to power awareness and required performance. To make use of this power-saving potential, also the higher layers of the system - the operating system layer and the application domain layer - are required to be designed together with the rest of the system. HW/SW co-design methodologies enable the gain of system-level optimization. The first part presents the abstraction of smart cards to optimize system architecture and memory system. Both functional and transactional-level models are presented and discussed. The proposed design flow and preliminary results of the evaluation are depicted. Another central part of this methodology is a cycle-accurate instruction-set simulator for secure software development. The underlaying energy model is designed to decouple instruction and data dependent energy dissipation, which leads to an independent characterization process and allows stepwise model refinement to increase estimation accuracy. The model has been evaluated for a high-performance smart card CPU and an use-case for secure software is given

System-level power optimization:techniques and tools

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software