Statistical communication theory Final report, 1 Dec. 1963 - 31 Mar. 1967

Research and scientific reports on statistical communication theor

A study of major coding techniques for digital communication Final report

Coding techniques for digital communication channel

Introduction to Forward-Error-Correcting Coding

This reference publication introduces forward error correcting (FEC) and stresses definitions and basic calculations for use by engineers. The seven chapters include 41 example problems, worked in detail to illustrate points. A glossary of terms is included, as well as an appendix on the Q function. Block and convolutional codes are covered

Versatile Error-Control Coding Systems

$NC research reported in this thesis is in the field of error-correcting codes, which has evolved as a very important branch of information theory. The main use of error-correcting codes is to increase the reliability of digital data transmitted through a noisy environment. There are, sometimes, alternative ways of increasing the reliability of data transmission, but coding methods are now competitive in cost and complexity in many cases because of recent advances in technology. The first two chapters of this thesis introduce the subject of error-correcting codes, review some of the published literature in this field and discuss the advan­tages of various coding techniques. After presenting linear block codes attention is from then on concentrated on cyclic codes, which is the subject of Chapter 3. The first part of Chapter 3 presents the mathemati­cal background necessary for the study of cyclic codes and examines existing methods of encoding and their practical implementation. In the second part of Chapter 3 various ways of decoding cyclic codes are studied and from these considerations, a general decoder for cyclic codes is devised and is presented in Chapter 4. Also, a review of the principal classes of cyclic codes is presented. Chapter 4 describes an experimental system constructed for measuring the performance of cyclic codes initially RC5GI5SCD by random errors and then by bursts of errors. Simulated channels are used both for random and burst errors. A computer simulation of the whole system was made in order to verify the accuracy of the experimental results obtained. Chapter 5 presents the various results obtained with the experimental system and by computer simulation, which allow a comparison of the efficiency of various cyclic codes to be made. Finally, Chapter 6 summarises and dis­cusses the main results of the research and suggests interesting points for future investigation in the area. The main objective of this research is to contribute towards the solution of a fairly wide range of problems arising in the design of efficient coding schemes for practical applications; i.e. a study of coding from an engineering point of view

Research in computer technology, spectrometry, control systems, vacuum instrumentation, plasma physics, superconductivity and related topics Progress report, Jun. - Aug. 1965

Research projects on surface and plasma physics, computer programming, information processing, superconductivity, ionospheric data, network synthesis and related field

Novel Methods in the Improvement of Turbo Codes and their Decoding

The performance of turbo codes can often be improved by improving the weight spectra of such codes. Methods of producing the weight spectra of turbo codes have been investigated and many improvements were made to refine the techniques. A much faster method of weight spectrum evaluation has been developed that allows calculation of weight spectra within a few minutes on a typical desktop PC. Simulation results show that new high performance turbo codes are produced by the optimisation methods presented. The two further important areas of concern are the code itself and the decoding. Improvements of the code are accomplished through optimisation of the interleaver and choice of constituent coders. Optimisation of interleaves can also be accomplished automatically using the algorithms described in this work. The addition of a CRC as an outer code proved to offer a vast improvement on the overall code performance. This was achieved without any code rate loss as the turbo code is punctured to make way for the CRC remainder. The results show a gain of 0.4dB compared to the non-CRC (1014,676) turbo code. Another improvement to the decoding performance was achieved through a combination of MAP decoding and Ordered Reliability decoding. The simulations show a performance of just 0.2dB from the Shannon limit. The same code without ordered reliability decoding has a performance curve which is 0.6dB from the Shannon limit. In situations where the MAP decoder fails to converge ordered reliability decoding succeeds in producing a codeword much closer to the received vector, often the correct codeword. The ordered reliability decoding adds to the computational complexity but lends itself to FPGA implementation.Engineering and Physical Sciences Research Council (EPSRC

REAL TIME MICROPROCESSOR TECHNIQUES FOR A DIGITAL MULTITRACK TAPE RECORDER

Transport properties of a standard compact - cassette tape system are measured and software techniques devised to configure a low - cost,direct digital recording system. Tape - velocity variation is typically ± 10% of standard speed over tape lengths of 5 µm.with occasional variations of ±40%. Static tape - skew can result due to axial movement of the tape reel when it spools.Dynamic tape skew occurs and is primarily caused by tape - edge curvature with a constant contribution due to the transport mechanism.Spectral skew components range from 0.32 Hz to 8 Hz with magnitude normally within one 10 kbit/ sec- bit cell.The pinch roller works against the friction of the tape guides to cause tape deformation.Average values of tape deformation are 0.67 µm,0.85 µm and 1.08 µm for C60,C90 and C120 tape respectively. Parallel,software encoding / decoding algorithms have been developed for several channel codes.Adaptive software methods permit track data rates up to 3.33 k bits/sec in a rnultitrack system using a simple microcomputer.For a 4 - track system,raw error rates vary from 10ˉ⁷ at 500 bits/sec/track to 10ˉ⁵ at 3.33 kbits/sec/track.Adaptive software reduces skew - induced errors by 50%.A skew - correction technique has been developed and implemented on an 8 - track system at a track data rate of 10 k bits/sec. Real - time error correction gives a theoretical corrected error rate of 10ˉ¹¹for a raw error rate of 10ˉ⁷. Multiple track errors can cause mis - correction and interleaving is advised. Software algorithms have been devised for Reed - Solomon code. With a more powerful microprocessor this code m ay be combined with the above techniques in a layered error-correction scheme. The software techniques developed may be applied to N tracks with an N - bit computer.Recording density may be increased by using thin - film,multitrack heads and a faster computer.British Broadcasting Corporatio

Index to 1986 NASA Tech Briefs, volume 11, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1986 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design