Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.Comment: 16 pages, 22 figures, 2 table

Fault Tolerance of Stochastic Decoders for Error Correcting Codes

Low-density Parity-check (LDPC) codes are very powerful linear error-correcting codes, first introduced by Gallager in 1963. They are now used in many communication standards due to their ability to achieve near Shannon-capacity performance. Stochastic decoding is a hardware-efficient method of iterative decoding of LDPC codes. In this work, we investigate the capability of stochastic decoding to tolerate circuit soft errors while maintaining good bit error rate performance and low error floor. Soft errors can be intended faults as a result of either supply voltage scaling to reduce power consumption or overclocking the system to achieve a higher throughput. They can also be unintended faults as a result of temperature or process variations. We develop two models to emulate these circuit errors at the system level. We apply our models to two standardized LDPC codes (10GBASE-T and WiMAX). Simulation results show that stochastic decoding is very tolerant to faults and errors, where it can tolerate a probability of setup time violation of 0.1 in the wires of the decoder. Hence, stochastic decoding can be very useful in systems with very low power or high performance requirements where we can push the limits of power or speed by lowering the supply voltage or highly overclocking the system while maintaining good performance. In addition, a chip has been designed and sent to fabrication to do post-silicon validation and verify our models

A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing

International audience—Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. In this paper a new hardware aware check node algorithm and its architecture is proposed. It has state-of-the-art communications performance while reducing the decoding complexity. The presented architecture has a 14 times higher area efficiency, increases the energy efficiency by factor 2.5 and reduces the latency by factor of 3.5 compared to a state-of-the-art architecture

Sequence codes

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Anuário Científico – 2011 Resumos de Artigos, Comunicações, Livros e Monografias de Mestrado

Há mais de uma década que o ISEL vem firmando a sua aposta na busca e na divulgação do conhecimento científico na área da Engenharia, assentes na inovação e no desenvolvimento de novas tecnologias, procurando que os resultados alcançados nos projetos de investigação tenham impacto na indústria e na vida dos cidadãos como forma de responder às necessidades cada vez mais complexas e exigentes da sociedade no seu todo. Nesta relação, o ISEL tem contribuído para a evolução da produção e do conhecimento científicos, assumindo, por vezes numa posição de vanguarda, ora em iniciativa própria ora em parceria com diversas instituições, quer de ensino quer do tecido empresarial. Como forma de dar visibilidade ao trabalho desenvolvido pelos docentes (com afiliação ISEL) e alunos do ISEL, o Anuário Científico tornou-se num meio de divulgação privilegiado, estando disponível em acesso livre a toda a comunidade científica mas também a todos os cidadãos, podendo ser consultado em formato eletrónico no sítio institucional do ISEL, bem como no Repositório Científico do Instituto Polítécnico de Lisboa.1 Fazendo uma análise comparativa em relação às publicações referentes a 2009 e a 2010, constata-se que o número de publicações duplicou em 2011