Advanced sensors technology survey

This project assesses the state-of-the-art in advanced or 'smart' sensors technology for NASA Life Sciences research applications with an emphasis on those sensors with potential applications on the space station freedom (SSF). The objectives are: (1) to conduct literature reviews on relevant advanced sensor technology; (2) to interview various scientists and engineers in industry, academia, and government who are knowledgeable on this topic; (3) to provide viewpoints and opinions regarding the potential applications of this technology on the SSF; and (4) to provide summary charts of relevant technologies and centers where these technologies are being developed

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Energy management techniques for ultra-small bio-medical implants

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 167-174).Trends in the medical industry have created a growing demand for implantable medical devices. In particular, the need to provide medical professionals a means to continuously monitor bio-markers over long time scales with increased precision is paramount to efficient healthcare. To make medical implants more attractive, there is a need to reduce their size and power consumption. Small medical implants would allow for less invasive procedures and greater comfort for patients. The two primary limitations to the size of small medical implants are the batteries that provide energy to circuit and sensor components, and the antennas that enable wireless communication to terminals outside of the body. In this work we present energy management and low-power techniques to help solve the engineering challenges posed by using ultracapacitors for energy storage. A major problem with using any capacitor as an energy source is the fact that its voltage drops rapidly with decreasing charge. This leaves the circuit to cope with a large supply variation and can lead to energy being left on the capacitor when its voltage gets too low to supply a sufficient supply voltage for operation. Rather than use a single ultracapacitor, we demonstrate higher energy utilization by splitting a single capacitor into an array of capacitors that are progressively reconfigured as energy is drawn out. An energy management IC fabricated in 180-nm CMOS implements a stacking procedure that allows for more than 98% of the initial energy stored in the ultracapacitors to be removed before the output voltage drops unsuitably low for circuit operation. The second part of this work develops techniques for wide-input-range energy management. The first chip implementing stacking suffered an efficiency penalty by using a switchedcapacitor voltage regulator with only a single conversion ratio. In a second implementation, we introduce a better solution that preserves efficiency performance by using a multiple conversion ratio switched-capacitor voltage regulator. At any given input voltage from an ultracapcitor array, the switched-capacitor voltage regulator is configured to maximize efficiency. Fabricated in a 180-nm CMOS process, the chip achieves a peak efficiency of 90% and the efficiency does not fall below 70% for input voltages between 1.25 and 3 V.by William R. Sanchez.Ph.D

Design and implementation of a multi-modal sensor with on-chip security

With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore\u27s law and the possibility of having a higher number of transistors and more complex circuits, the feasibility of having on-chip security measures is drawing more attention. One of the fundamental means of secure communication is real-time encryption. Encryption/ciphering occurs when we encode a signal or data, and prevents unauthorized parties from reading or understanding this information. Encryption is the process of transmitting sensitive data securely and with privacy. This measure of security is essential since in biomedical devices, the attacker/hacker can endanger users of IoT or wearable sensors (e.g. attacks at implanted biosensors can cause fatal harm to the user). This work develops 1) A low power and compact multi-modal sensor that can measure temperature and impedance with a quasi-digital output and 2) a low power on-chip signal cipher for real-time data transfer

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

Low power CMOS IC, biosensor and wireless power transfer techniques for wireless sensor network application

The emerging field of wireless sensor network (WSN) is receiving great attention due to the interest in healthcare. Traditional battery-powered devices suffer from large size, weight and secondary replacement surgery after the battery life-time which is often not desired, especially for an implantable application. Thus an energy harvesting method needs to be investigated. In addition to energy harvesting, the sensor network needs to be low power to extend the wireless power transfer distance and meet the regulation on RF power exposed to human tissue (specific absorption ratio). Also, miniature sensor integration is another challenge since most of the commercial sensors have rigid form or have a bulky size. The objective of this thesis is to provide solutions to the aforementioned challenges

Bioelectronics for Amperometric Biosensors

The Discrete-to-Integrated Electronics group (D2In), at the University of Barcelona, in partnership with the Bioelectronics and Nanobioengineering Group (SICBIO), is researching Smart Self-Powered Bio-Electronic Systems. Our interest is focused on the development of custom built electronic solutions for bio-electronics applications, from discrete devices to Application-specific integrated circuit (ASIC) solutions. The integration of medical and electronic technologies allows the development of biomedical devices able to diagnose and/or treat pathologies by detecting and/or monitoring pathogens, multiple ions, PH changes, and so on. Currently this integration enables advances in various areas such as microelectronics, microfluidics, microsensors and bio-compatible materials which open the door to developing human body Lab-on-a-Chip implantable devices, Pointof- Care in vitro devices, etc. In this chapter the main attention is focused on the design of instrumentation related to amperometrics biosensor: biopotentiostat amplifiers and lock-in amplifiers. A potentiostat is a useful tool in many fields of investigation and industry performing electrochemical trials [1], so the quantity and variety of them is very extensive. Since they can be used in studies and targets as different as the study of chemical metal conversions [2] or carcinogenic cells detection, neuronal activity detection or Deoxyribonucleic acid (DNA) recognition, their characteristics are very varied..