Spaceborne P-Band MIMO SAR for Planetary Applications

The Space Exploration Synthetic Aperture Radar (SESAR) is an advanced P-band beamforming radar instrument concept to enable a new class of observations suitable to meet Decadal Survey science goals for planetary exploration. The radar operates at full polarimetry and fine (meter scale) resolution, and achieves beam agility through programmable waveform generation and digital beamforming. The radar architecture employs a novel low power, lightweight design approach to meet stringent planetary instrument requirements. This instrument concept has the potential to provide unprecedented surface and near-subsurface measurements applicable to multiple Decadal Survey Science Goals

Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0

Journal ArticleA significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire models (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model Non-uniform Cache Access (NUCA). We not only adopt state-of-the-art design space exploration strategies for NUCA, we also enhance this exploration by considering on-chip network contention and a wider spectrum of wiring and routing choices. We present a validation analysis of the new tool (to be released as CACTI 6.0) and present a case study to showcase how the tool can improve architecture research methodologies

Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0

Journal ArticleA significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire models (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model Non-uniform Cache Access (NUCA). We not only adopt state-of-the-art design space exploration strategies for NUCA, we also enhance this exploration by considering on-chip network contention and a wider spectrum of wiring and routing choices. We present a validation analysis of the new tool (to be released as CACTI 6.0) and present a case study to showcase how the tool can improve architecture research methodologies

Beamforming P-Band Synthetic Aperture Radar for Planetary Applications

The Space Exploration Synthetic Aperture Radar (SESAR) is an advanced P-band beamforming radar instrument concept to enable a new class of observations suitable to meet multiple Decadal Survey science goals for planetary exploration. The radar is capable of providing unprecedented surface and near subsurface measurements at full polarimetry and fine (meter scale) resolution, and achieves beam agility through programmable waveform generation and digital beamforming. The radars highly flexible modular architecture employs a novel low power, lightweight design approach to meet stringent planetary instrument requirements, all while minimizing cost and development time

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios

Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications

The fifth-generation (5G) revolution represents more than a mere performance enhancement of previous generations: it will deeply transform the way humans and/or machines interact, enabling a heterogeneous expansion in the number of use cases and services. Crucial to the realization of this revolution is the design of hardware components characterized by high degrees of flexibility, versatility and resource/power efficiency. This chapter proposes a field-programmable gate array (FPGA)-oriented baseband processing architecture suitable for fast-changing communication environments such as 4G/5G waveform coexistence, noncontiguous carrier aggregation (CA) or centralized cloud radio access network (C-RAN) processing. The proposed architecture supports three 5G waveform candidates and is shown to be upgradable, resource-efficient and cost-effective. Through hardware virtualization, enabled by dynamic partial reconfiguration (DPR), the design space exploration of our architecture exceeds the hardware resources available on the Zynq xc7z020 device. Moreover, dynamic frequency scaling (DFS) enables the runtime adjustment of processing throughput and power reductions by up to 88%. The combined resource overhead for DPR and DFS is very low, and the reconfiguration latency stays two orders of magnitude below the control plane latency requirements proposed for 5G communications

Lunar Propellant Factory Mission Design To Sustain Future Human Exploration

The International Space Exploration Coordination Group (ISECG) Global Exploration Roadmap (GER) is the standard document reflecting the current focus of the leading space agencies that envision space exploration missions beyond Low Earth Orbit (LEO), returning to the Moon and going to Mars in the upcoming years. The roadmap showcases the Moon as a stepping-stone for further human space exploration, by setting up a sustainable space infrastructure on its surface an orbit. Inspired from this vision, we present the result of a phase A study about a lunar propellant factory near the Shackleton south-pole crater relying on In-Situ Resources Utilization (ISRU) to produce and sell Liquid Oxygen (LOX) on the moon surface and in orbit. The overall timeline of the mission is in line with the ISECG exploration roadmap Moon phase, based on realistic technologies of advanced-enough Technology Readiness Levels (TRL). It is a second iteration on the Lunar Propellant Outpost (LUPO) mission architecture, presented during IAC 2018. We preserved and reviewed the original building blocks (Habitats, Crew Mobility Elements, ISRU Facilities, and Lunar Spaceport) of the LUPO mission architecture, and further improved the mission design, supported by trade-off analysis on different mission scenarios. An extensive analysis and optimisation have been performed on ISRU processes and surface electrical power management, the core of our infrastructure. The mission architecture also includes crew on the lunar surface, so life support systems and habitat, as well as operations concepts, have been studied in-depth, and a synthesis of all results is presented. The main aim of this iteration was to improve and refine the baseline infrastructural and technological design architecture of LUPO and reflect on missions going beyond the Moon by providing refuelling services, with sustainability and economic viability in mind

Overview of the Development and Mission Application of the Advanced Electric Propulsion System (AEPS)

NASA remains committed to the development and demonstration of a high-power solar electric propulsion capability for the Agency. NASA is continuing to develop the 14 kilowatt Advanced Electric Propulsion System (AEPS), which has recently completed an Early Integrated System Test and System Preliminary Design Review. NASA continues to pursue Solar Electric Propulsion (SEP) Technology Demonstration Mission partners and mature high-power SEP mission concepts. The recent announcement of the development of a Power and Propulsion Element (PPE) as the first element of an evolvable human architecture to Mars has replaced the Asteroid Redirect Robotic Mission as the most probable first application of the AEPS Hall thruster system. This high-power SEP capability, or an extensible derivative of it, has been identified as a critical part of an affordable, beyond-low-Earth-orbit, manned-exploration architecture. This paper presents the status of the combined NASA and Aerojet AEPS development activities and updated mission concept for implementation of the AEPS hardware as part of the ion propulsion system for a PPE

ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks

The Convolutional Neural Network (CNN) has emerged as a powerful and versatile tool for artificial intelligence (AI) applications. Conventional computing architectures face challenges in meeting the demanding processing requirements of compute-intensive CNN applications, as they suffer from limited throughput and low utilization. To this end, specialized accelerators have been developed to speed up CNN computations. However, as we demonstrate in this paper via extensive design space exploration, different neural network models have different characteristics, which calls for different accelerator architectures and configurations to match their computing demand. We show that a one-size-fits-all fixed architecture does not guarantee optimal power/energy/performance trade-off. To overcome this challenge, this paper proposes ARMAN, a novel reconfigurable systolic-array-based accelerator architecture based on Monolithic 3D (M3D) technology for CNN inference. The proposed accelerator offers the flexibility to reconfigure among different scale-up or scale-out arrangements depending on the neural network structure, providing the optimal trade-off across power, energy, and performance for various neural network models. We demonstrate the effectiveness of our approach through evaluations of multiple benchmarks. The results demonstrate that the proposed accelerator exhibits up to 2x, 2.24x, 1.48x, and 2x improvements in terms of execution cycles, power, energy, and EDP respectively, over the non-configurable architecture