Monolithically Patterned Wide-Narrow-Wide All-Graphene Devices

We investigate theoretically the performance advantages of all-graphene nanoribbon field-effect transistors (GNRFETs) whose channel and source/drain (contact) regions are patterned monolithically from a two-dimensional single sheet of graphene. In our simulated devices, the source/drain and interconnect regions are composed of wide graphene nanoribbon (GNR) sections that are semimetallic, while the channel regions consist of narrow GNR sections that open semiconducting bandgaps. Our simulation employs a fully atomistic model of the device, contact and interfacial regions using tight-binding theory. The electronic structures are coupled with a self-consistent three-dimensional Poisson's equation to capture the nontrivial contact electrostatics, along with a quantum kinetic formulation of transport based on non-equilibrium Green's functions (NEGF). Although we only consider a specific device geometry, our results establish several general performance advantages of such monolithic devices (besides those related to fabrication and patterning), namely the improved electrostatics, suppressed short-channel effects, and Ohmic contacts at the narrow-to-wide interfaces.Comment: 9 pages, 11 figures, 2 table

Model of tunneling transistors based on graphene on SiC

Recent experiments shown that graphene epitaxially grown on Silicon Carbide (SiC) can exhibit a energy gap of 0.26 eV, making it a promising material for electronics. With an accurate model, we explore the design parameter space for a fully ballistic graphene-on-SiC Tunnel Field-Effect Transistors (TFETs), and assess the DC and high frequency figures of merit. The steep subthreshold behavior can enable I_{ON}/I_{OFF} ratios exceeding 10^4 even with a low supply voltage of 0.15 V, for devices with gatelength down to 30 nm. Intrinsic transistor delays smaller than 1 ps are obtained. These factors make the device an interesting candidate for low-power nanoelectronics beyond CMOS

Reconfigurable nanoelectronics using graphene based spintronic logic gates

This paper presents a novel design concept for spintronic nanoelectronics that emphasizes a seamless integration of spin-based memory and logic circuits. The building blocks are magneto-logic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and present a spin-based circuit design with smaller area, faster speed, and lower energy consumption than the state-of-the-art CMOS counterparts. This design can also be applied in applications such as data compression, coding and image recognition. In the proposed scheme, over 100 spin-based logic operations are carried out before any need for a spin-charge conversion. Consequently, supporting CMOS electronics requires little power consumption. The spintronic-CMOS integrated system can be implemented on a single 3-D chip. These nonvolatile logic circuits hold potential for a paradigm shift in computing applications.Comment: 14 pages (single column), 6 figure

Hysteresis in As-Synthesized MoS2 Transistors: Origin and Sensing Perspectives

Two-dimensional materials, including molybdenum disulfide (MoS2), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. However, these materials still exhibit integration difficulties with complementary-MOS standardized processes and methods. The device reliability is compromised by gate insulator selection and the quality of the metal/semiconductor and semiconductor/insulator interfaces. Despite some improvements regarding mobility, hysteresis and Schottky barriers having been reported thanks to metal engineering, vertically stacked heterostructures with compatible thin-layers (such as hexagonal boron nitride or device encapsulation) variability is still an important constraint to sensor performance. In this work, we fabricated and extensively characterized the reliability of as-synthesized back-gated MoS2 transistors. Under atmospheric and room-temperature conditions, these devices present a wide electrical hysteresis (up to 5 volts) in their transfer characteristics. However, their performance is highly influenced by the temperature, light and pressure conditions. The singular signature in the time response of the devices points to adsorbates and contaminants inducing mobile charges and trapping/detrapping carrier phenomena as the mechanisms responsible for time-dependent current degradation. Far from being only a reliability issue, we demonstrated a method to exploit this device response to perform light, temperature and/or pressure sensors in as-synthesized devices. Two orders of magnitude drain current level differences were demonstrated by comparing device operation under light and dark conditions while a factor up to 105 is observed at vacuum versus atmospheric pressure environments.European Union’s Horizon 2020 Research and Innovation Programme under the Marie Skłodowska-Curie grant agreement No 895322Spanish Government under Juan de la Cierva Formacion grant number FJC2018-038264-ISpanish Ministry of Economy, Industry and Competitivity under grant TEC2017-89800-RASCENT (EU Horizon 2020 GRANT 654384)Science Foundation Ireland through the AMBER 2 project (12/RC/2278-P2)UGR-MADOC CEMIX 2D-EDE

Development of electrochromic thin-film transistors on flexible substrate

This work documents the fabrication and characterization of electrochromic thin-film transistors (ECTFTs) based on tungsten oxide (WO3). The ECTFTs exhibit double functionality (optical and electrical modulation) and were deposited on Corning glass and polyethylene naphthalate (PEN) by radio-frequency (RF) magnetron sputtering in an argon-oxygen atmospherewith no intentional substrate heating. The resulting amorphous WO3film connects source and drain in a planar configuration with three different architectures(conventional, interdigital and back-electrode) and isgated by a drop-casted lithium-based polymer electrolyte (LiClO4:PC). EC films were characterized using X-ray diffraction (XRD), atomic force microscopy (AFM)andopto-electrochemical measurements, the electrolyte by electrochemicalimpedance spectroscopy (EIS) and the ECTFTs by static and dynamic electrical characterization. Thinner EC films (75 nm) evidenced lower optical density (ΔOD) and color efficiency (CE) of 0,26 and 21,85 cm2C-1, respectively, but faster EC reaction kinetics, with bleaching and coloration times (tband tc) of 1,8 and 3,8 seconds, respectively. In terms of electrical properties the best performing ECTFT architecture (interdigital) showed an ION/IOFFof 2,81x105and a transconductance of 2,24 mS. The back-electrode architecturehowever showed better ionic movement control in the channel(adjustable VON)with enhanced colorations, making ita better candidate for a two-in-one (pixel + transistor) solution for display applications

Fault Modeling of Graphene Nanoribbon FET Logic Circuits

[EN] Due to the increasing defect rates in highly scaled complementary metal-oxide-semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.This work was supported in part by the Spanish Government under the research project TIN2016-81075-R and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), under the project 200190032.Gil Tomás, DA.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil, P. (2019). Fault Modeling of Graphene Nanoribbon FET Logic Circuits. Electronics. 8(8):1-18. https://doi.org/10.3390/electronics8080851S11888International Technology Roadmap for Semiconductors (ITRS) 2013http://www.itrs2.net/2013-itrs.htmlSchuegraf, K., Abraham, M. C., Brand, A., Naik, M., & Thakur, R. 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A Millimeter-scale Single Charged Particle Dosimeter for Cancer Radiotherapy

This paper presents a millimeter-scale CMOS 64$\times$64 single charged particle radiation detector system for external beam cancer radiotherapy. A 1$\times$1 $\mu m^2$ diode measures energy deposition by a single charged particle in the depletion region, and the array design provides a large detection area of 512$\times$512 $\mu m^2$. Instead of sensing the voltage drop caused by radiation, the proposed system measures the pulse width, i.e., the time it takes for the voltage to return to its baseline. This obviates the need for using power-hungry and large analog-to-digital converters. A prototype ASIC is fabricated in TSMC 65 nm LP CMOS process and consumes the average static power of 0.535 mW under 1.2 V analog and digital power supply. The functionality of the whole system is successfully verified in a clinical 67.5 MeV proton beam setting. To our' knowledge, this is the first work to demonstrate single charged particle detection for implantable in-vivo dosimetry

Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range. Our data suggest that, for application processors operating between 20{\deg}C and 50{\deg}C, a quadratic model is still accurate and a linear approximation is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV