DRAM을 위한 오프셋 캔슬링 센스 앰플리파이어의 설계와 오프셋 캔슬링 방법에 관한 분석

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis reports the offset issues of the sense amplifiers for DRAM (dynamic random-access memory) due to scaling-down of the devices. An offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors. Analytical calculations of the average and standard deviation of the decision threshold voltages, defined as the voltage in the cell capacitor that bifurcates into binary levels when activated, are performed on various DRAM sensing schemes and their comparison results are presented. Based on the analysis, the proposed sense amplifier scheme using coupling capacitors is shown to offer the least amount of variation in the decision threshold, thereby increasing the sensing margin of the overall DRAM design. The coupling capacitors not only compensate for the random offset of the sense amplifiers, but also mitigate the effect of the mismatch of the bitline capacitances in the open bit line scheme. Measurement on the experimental chip fabricated in 65nm CMOS process validates the analysis and confirms superior performance of the proposed DRAM sensing scheme. Furthermore, it presents a gate voltage controlling scheme to reduce the offset due to pro-cess variation and a crosstalk canceling scheme to compensate for the data-dependent offsets.이 논문은 장치의 축소로 인한 DRAM (동적 랜덤 액세스 메모리) 용 감지 증폭기 (sense amplifier)의 오프셋 문제를 보고하고 이에 대해 분석합니다. 증폭 트랜지스터의 임계 전압 (threshold voltage) 의 무작위 변화 (random variation)로 인해 발생하는 오프셋을 저장 및 보상하기위한 커플링 커패시터 (coupling capacitor)가 있는 오프셋 보상 DRAM 감지 증폭기를 제안합니다. 셀 커패시터의 전압으로 정의되는 결정 임계 전압의 평균 및 표준 편차에 대한 분석 및 계산이 다양한 DRAM 감지 증폭기 방식에서 수행되며 비교 결과가 제공됩니다. 분석에 따르면, 커플링 커패시터를 사용하는 제안 된 감지 증폭기 방식은 결정 임계 값의 변동을 최소화하여 전체 DRAM 설계의 감지 마진을 증가시키는 것으로 나타났습니다. 커플링 커패시터는 감지 증폭기의 랜덤 오프셋을 보상 할뿐만 아니라 개방형 비트 라인 (open-bitline) 방식에서 비트 라인 커패시턴스의 불일치 효과를 완화합니다. 65nm CMOS 공정으로 제작 된 실험용 칩에 대한 측정은 분석을 검증하고 제안 된 DRAM 감지 방식의 우수한 성능을 확인합니다. 또한 프로세스 변동으로 인한 오프셋을 줄이기위한 게이트 전압 제어 방식과 데이터 의존적 오프셋을 보상하기위한 크로스 토크(crosstalk) 제거 방식을 제안합니다.ABSTRACT I CONTENTS II LIST OF FIGURES VI LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUND ON DRAM SENSE AMPLIFIERS 5 2.1 OVERVIEW 5 2.2 BASICS OF DRAM SENSE AMPLIFIERS 6 2.2.1 SENSE AMPLIFIER AND CORE STRUCTURE 6 2.2.2 READ OPERATION 9 2.3 DESIGN CHALLENGES FOR SENSE AMPLIFIER 12 2.3.1 SCALING-DOWN ISSUE AND SENSING MARGIN 12 2.3.2 SENSING TIME AND LAYOUT 15 CHAPTER 3 OFFSET MODELING AND ANALYSIS 17 3.1 OVERVIEW 17 3.2 TYPES OF OFFSETS 18 3.2.1 PROCESS VARIATION 18 3.2.2 INTRINSIC OFFSET 19 3.2.3 DATA-DEPENDENT OFFSET 20 3.3 OFFSET MODELS 22 3.3.1 LATCH SENSING TRAJECTORY 23 3.3.2 METASTABLE POINT 26 3.3.3 SENSING OFFSET 28 3.3.4 DECISION THRESHOLD VOLTAGE AND SENSING MARGIN 30 CHAPTER 4 ANALYSIS ON OFFSET-CANCELING SENSE AMPLIFIERS 32 4.1 OVERVIEW 32 4.2 COMPARISON ANALYSIS 35 4.3 CONVENTIONAL SENSE AMPLIFIER 36 4.4 OFFSET MISMATCH CALIBRATION SENSE AMPLIFIER 37 4.4.1 BITLINE SEPARATION SCHEME 39 4.5 OFFSET-CANCELING SENSE AMPLIFIER 43 4.5.1 RELATIONSHIP BETWEEN OMC AND OC 46 4.5.2 PRE-SENSING 48 CHAPTER 5 CAPACITOR-COUPLED OFFSET-CANCELED SENSE AMPLIFIER 51 5.1 OVERVIEW 51 5.2 MATHEMATICAL ANALYSIS 53 5.3 MONTE-CARLO SIMULATION RESULTS 55 5.4 EXPERIMENTAL RESULTS 61 CHAPTER 6 GATE VOLTAGE CONTROL SCHEME FOR PROCESS VARIATIONS 65 6.1 OVERVIEW 65 6.2 ARCHITECTURE 67 6.2.1 DIFFERENTIAL AMPLIFIER 67 6.2.2 OPERATIONAL AMPLIFIER (OP-AMP) 68 6.2.3 REPLICA SENSE AMPLIFIER 68 6.2.4 PMOS INVERTER 69 6.2.5 LOW DROPOUT VOLTAGE REGULATOR 69 6.2.6 BIAS GENERATOR 69 6.2.7 SENSE AMPLIFIER 70 6.2.8 LOOK-UP TABLE (LUT) 70 6.3 EFFECT OF GATE VOLTAGE CONTROL SCHEME 73 6.3.1 BEHAVIORAL MODELING 73 6.3.2 SIMULATION RESULTS 77 CHAPTER 7 CROSSTALK CANCELING SCHEME FOR DATA-DEPENDENT OFFSET CANCELATION 78 7.1 OVERVIEW 78 7.2 CROSSTALK EFFECTS 80 7.3 CROSSTALK CANCELING SCHEME 82 7.3.1 IMPLEMENTATION 82 7.3.2 EFFECT OF THE CROSSTALK CANCELING SCHEME 84 7.3.3 SIMULATION RESULTS 86 CHAPTER 8 CONCLUSION 88 BIBLIOGRAPHY 90 초 록 92Docto

A Process Variation Tolerant Self-Compensation Sense Amplifier Design

As we move under the aegis of the Moore\u27s law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node

Design and Robustness Analysis on Non-volatile Storage and Logic Circuit

By combining the flexibility of MOS logic and the non-volatility of spintronic devices, spin-MOS logic and storage circuitry offer a promising approach to implement highly integrated, power-efficient, and nonvolatile computing and storage systems. Besides the persistent errors due to process variations, however, the functional correctness of Spin-MOS circuitry suffers from additional non-persistent errors that are incurred by the randomness of spintronic device operations, i.e., thermal fluctuations. This work quantitatively investigates the impact of thermal fluctuations on the operations of two typical Spin-MOS circuitry: one transistor and one magnetic tunnel junction (1T1J) spin-transfer torque random access memory (STT-RAM) cell and a nonvolatile latch design. A new nonvolatile latch design is proposed based on magnetic tunneling junction (MTJ) devices. In the standby mode, the latched data can be retained in the MTJs without consuming any power. Two types of operation errors can occur, namely, persistent and non-persistent errors. These are quantitatively analyzed by including models for process variations and thermal fluctuations during the read and write operations. A mixture importance sampling methodology is applied to enable yield-driven design and extend its application beyond memories to peripheral circuits and logic blocks. Several possible design techniques to reduce thermal induced non-persistent error rate are also discussed

Circuit Techniques for Adaptive and Reliable High Performance Computing.

Increasing power density with process scaling has caused stagnation in the clock speed of modern microprocessors. Accordingly, designers have adopted message passing and shared memory based multicore architectures in order to keep up with the rapidly rising demand for computing throughput. At the same time, applications are not entirely parallel and improving single-thread performance continues to remain critical. Additionally, reliability is also worsening with process scaling, and margining for failures due to process and environmental variations in modern technologies consumes an increasingly large portion of the power/performance envelope. In the wake of multicore computing, reliability of signal synchronization between the cores is also becoming increasingly critical. This forces designers to search for alternate efficient methods to improve compute performance while addressing reliability. Accordingly, this dissertation presents innovative circuit and architectural techniques for variation-tolerance, performance and reliability targeted at datapath logic, signal synchronization and memories. Firstly, a domino logic based design style for datapath logic is presented that uses Adaptive Robustness Tuning (ART) in addition to timing speculation to provide up to 71% performance gains over conventional domino logic in 32bx32b multiplier in 65nm CMOS. Margins are reduced until functionality errors are detected, that are used to guide the tuning. Secondly, for signal synchronization across clock domains, a new class of dynamic logic based synchronizers with single-cycle synchronization latency is presented, where pulses, rather than stable intermediate voltages cause metastability. Such pulses are amplified using skewed inverters to improve mean time between failures by ~1e6x over jamb latches and double flip-flops at 2GHz in 65nm CMOS. Thirdly, a reconfigurable sensing scheme for 6T SRAMs is presented that employs auto-zero calibration and pre-amplification to improve sensing reliability (by up to 1.2 standard deviations of NMOS threshold voltage in 28nm CMOS); this increased reliability is in turn traded for ~42% sensing speedup. Finally, a main memory architecture design methodology to address reliability and power in the context of Exascale computing systems is presented. Based on 3D-stacked DRAMs, the methodology co-optimizes DRAM access energy, refresh power and the increased cost of error resilience, to meet stringent power and reliability constraints.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107238/1/bharan_1.pd

공정 변화에 둔감한 자동 온도 보상 셀프 리프레쉬용 모바일 디램 온도계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 김수환.Smaller transistors mean that capacitors are charged less uniformly, which increases the self-refresh current in the DRAMs used in mobile devices. Adaptive self-refresh using an on-chip thermometer can solve this problem. In this thesis, a PVT tolerant on-chip CMOS thermometer specifically designed for controlling the refresh period of a DRAM will be proposed for low power mobile DRAM. Two types of on-chip CMOS thermometer including a novel temperature sensor is proposed, which is implemented in two different DRAM process technologies integrated into mobile LPDDR2 and LPDDR3 products. The on-chip thermometer incorporating in mobile LPDDR2 chip is fabricated in a 44nm DRAM process with a supply of 1.1V. The sensor has a temperature sensitivity of −3.2mV/°C, over a range of 0°C to 110°C. Its resolution is 1.94°C and is only limited by the 6.2mV step of the associated resistor ladder not by its own design. The high linearity of the sensor permits one-point calibration, after which the errors in 61 sample circuits ranged between −1.42°C and +2.66°C. The sensor has an active area of 0.001725mm2 and consumes less than 0.36μW on average with a supply of 1.1V. To improve the overall performance including ultra-low operation voltage, temperature sensitivity, low power consumption, high linearity regardless of process skew variations and high productivity improved by one point calibration, the folded type on-chip thermometer incorporating in mobile LPDDR3 chip which fabricated in a 29nm DRAM process with a supply of 1.1V and 0.8V will be proposed. This folded type sensor exhibits further upgrading properties such as a temperature sensitivity of −3.2mV/°[email protected] &−3.13mV/°C @0.8V, over wide range of -40°C to 110°C. Its resolution is 1.85°[email protected] & 1.98°[email protected] and is only limited by the 6.2mV step. The more linearity of folded type sensor permits one-point calibration, after which the errors in 494 sample circuits ranged between −1.94°C and +1.61°C. The folded type sensor has an active area of 0.001606mm2 and consumes less than 0.19μ[email protected] & 0.14μ[email protected] on average slightly more than unfolded type sensor.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 ARCHITECTURE OF THERMOMETER 5 2.1 INTRODUCTION TO ON-CHIP THERMOMETER IN MOBILE DRAM 5 2.2 PROPOSED ON-CHIP CMOS THERMOMETER ARCHITECTURE 17 2.3 TEMPERATURE READOUT PROCEDURE OF PROPOSED ON-CHIP CMOS THERMOMETER 23 2.4 PROPOSED FOLDED TYPE ON-CHIP CMOS THERMOMETER ARCHITECTURE 25 2.5 TEMPERATURE READOUT PROCEDURE OF PROPOSED FOLDED TYPE ON-CHIP CMOS THERMOMETER 30 2.6 ONE-POINT CALIBRATION METHOD 32 2.7 TEMPERATURE LINEARITY OF TEMPERATURE SENSOR 35 CHAPTER 3 OPERATIONAL PRINCIPLES OF CMOS TEMPERATURE SENSOR IN MOBILE DRAM 39 3.1 PRIOR WORKS OF ON-CHIP THERMOMETER 39 3.2 PROPOSED CMOS TEMPERATURE SENSOR IN MOBILE DRAM 44 3.3 OPERATION PRINCIPLES OF PROPOSED TEMPERATURE SENSOR 48 3.4 PROPOSED FOLDED TYPE TEMPERATURE SENSOR 55 CHAPTER 4 PERIPHERAL CIRCUITS OF THERMOMETER 60 4.1 REGULATOR FOR VLTCSR SUPPLY 61 4.1.1 DC ANALYSIS 62 4.1.2 AC ANALYSIS 63 4.2 RESISTOR DECK 67 4.3 COMPARATOR 68 CHAPTER 5 EXPERIMENTAL RESULTS 70 5.1 ON-CHIP CMOS THERMOMETER IN 44NM CMOS PROCESS FOR MOBILE LPDDR2 74 5.2 FOLDED TYPE ON-CHIP CMOS THERMOMETER IN 29NM CMOS PROCESS FOR MOBILE LPDDR3 77 CHAPTER 6 CONCLUSIONS 83 BIBLIOGRAPHY 86 ABSTRACT IN KOREAN 89Docto

Understanding and Improving the Latency of DRAM-Based Memory Systems

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems. Increasing core counts, and the emergence of increasingly more data-intensive and latency-critical applications further stress the importance of providing low-latency memory access. In this dissertation, we identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we present a series of new techniques. Our new techniques significantly improve both system performance and energy efficiency. We also examine the critical relationship between supply voltage and latency in modern DRAM chips and develop new mechanisms that exploit this voltage-latency trade-off to improve energy efficiency. The key conclusion of this dissertation is that augmenting DRAM architecture with simple and low-cost features, and developing a better understanding of manufactured DRAM chips together lead to significant memory latency reduction as well as energy efficiency improvement. We hope and believe that the proposed architectural techniques and the detailed experimental data and observations on real commodity DRAM chips presented in this dissertation will enable development of other new mechanisms to improve the performance, energy efficiency, or reliability of future memory systems.Comment: PhD Dissertatio

Improving Phase Change Memory (PCM) and Spin-Torque-Transfer Magnetic-RAM (STT-MRAM) as Next-Generation Memories: A Circuit Perspective

In the memory hierarchy of computer systems, the traditional semiconductor memories Static RAM (SRAM) and Dynamic RAM (DRAM) have already served for several decades as cache and main memory. With technology scaling, they face increasingly intractable challenges like power, density, reliability and scalability. As a result, they become less appealing in the multi/many-core era with ever increasing size and memory-intensity of working sets. Recently, there is an increasing interest in using emerging non-volatile memory technologies in replacement of SRAM and DRAM, due to their advantages like non-volatility, high device density, near-zero cell leakage and resilience to soft errors. Among several new memory technologies, Phase Change Memory (PCM) and Spin-Torque-Transfer Magnetic-RAM (STT-MRAM) are most promising candidates in building main memory and cache, respectively. However, both of them possess unique limitations that preventing them from being effectively adopted. In this dissertation, I present my circuit design work on tackling the limitations of PCM and STT-MRAM. At bit level, both PCM and STT-MRAM suffer from excessive write energy, and PCM has very limited write endurance. For PCM, I implement Differential Write to remove large number of unnecessary bit-writes that do not alter the stored data. It is then extended to STT-MRAM as Early Write Termination, with specific optimizations to eliminate the overhead of pre-write read. At array level, PCM enjoys high density but could not provide competitive throughput due to its long write latency and limited number of read/write circuits. I propose a Pseudo-Multi-Port Bank design to exploit intra-bank parallelism by recycling and reusing shared peripheral circuits between accesses in a time-multiplexed manner. On the other hand, although STT-MRAM features satisfactory throughput, its conventional array architecture is constrained on density and scalability by the pitch of the per-column bitline pair. I propose a Common-Source-Line Array architecture which uses a shared source-line along the row, essentially leaving only one bitline per column. For these techniques, I provide circuit level analyses as well as architecture/system level and/or process/device level discussions. In addition, relevant background and work are thoroughly surveyed and potential future research topics are discussed, offering insights and prospects of these next-generation memories

Modeling and design of high speed SRAM based memory chip

SRAM is used as Cache memory which is very fast and used to speed up the task of processor and memory interface. With improvements in VLSI technology, processor speeds have increased. The improvements in SRAM speed of operation with increased integration, bigger sizes, technology shrinking and power dissipation is required to match with improved processor. 2kb SRAM block is designed and tested for proper read and write operation. The single SRAM cell, the 32x32 memory array, along with the decoder circuit, the sense enable and write enable logic, are placed out. The different critical paths of the system, comprising of the row and the column decoder, the column mux and the read-write circuits are recognized and sized to meet the target specifications. Simple model for distributed interconnect delays, is introduced and verified by Cadence simulations, their necessity is demonstrated. The models for the delay of a SRAM are used to determine the array sizes for a SRAM. An analytical delay model is proposed to predict the block size for SRAM; proposed model is based on dynamic strategies for word line charging and bit line discharging. Novel Sense Amplifier (SA) circuit for 2kb SRAM is presented and analyzed in this work. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of the current controlled SA. Butterfly architecture that is central decoding scheme is used to make a 2kb block from 1kb, after simulations, the maximum operating frequency of the system was found to be 800MHz

Reliable Low-Power High Performance Spintronic Memories

Moores Gesetz folgend, ist es der Chipindustrie in den letzten fünf Jahrzehnten gelungen, ein explosionsartiges Wachstum zu erreichen. Dies hatte ebenso einen exponentiellen Anstieg der Nachfrage von Speicherkomponenten zur Folge, was wiederum zu speicherlastigen Chips in den heutigen Computersystemen führt. Allerdings stellen traditionelle on-Chip Speichertech- nologien wie Static Random Access Memories (SRAMs), Dynamic Random Access Memories (DRAMs) und Flip-Flops eine Herausforderung in Bezug auf Skalierbarkeit, Verlustleistung und Zuverlässigkeit dar. Eben jene Herausforderungen und die überwältigende Nachfrage nach höherer Performanz und Integrationsdichte des on-Chip Speichers motivieren Forscher, nach neuen nichtflüchtigen Speichertechnologien zu suchen. Aufkommende spintronische Spe- ichertechnologien wie Spin Orbit Torque (SOT) und Spin Transfer Torque (STT) erhielten in den letzten Jahren eine hohe Aufmerksamkeit, da sie eine Reihe an Vorteilen bieten. Dazu gehören Nichtflüchtigkeit, Skalierbarkeit, hohe Beständigkeit, CMOS Kompatibilität und Unan- fälligkeit gegenüber Soft-Errors. In der Spintronik repräsentiert der Spin eines Elektrons dessen Information. Das Datum wird durch die Höhe des Widerstandes gespeichert, welche sich durch das Anlegen eines polarisierten Stroms an das Speichermedium verändern lässt. Das Prob- lem der statischen Leistung gehen die Speichergeräte sowohl durch deren verlustleistungsfreie Eigenschaft, als auch durch ihr Standard- Aus/Sofort-Ein Verhalten an. Nichtsdestotrotz sind noch andere Probleme, wie die hohe Zugriffslatenz und die Energieaufnahme zu lösen, bevor sie eine verbreitete Anwendung finden können. Um diesen Problemen gerecht zu werden, sind neue Computerparadigmen, -architekturen und -entwurfsphilosophien notwendig. Die hohe Zugriffslatenz der Spintroniktechnologie ist auf eine vergleichsweise lange Schalt- dauer zurückzuführen, welche die von konventionellem SRAM übersteigt. Des Weiteren ist auf Grund des stochastischen Schaltvorgangs der Speicherzelle und des Einflusses der Prozessvari- ation ein nicht zu vernachlässigender Zeitraum dafür erforderlich. In diesem Zeitraum wird ein konstanter Schreibstrom durch die Bitzelle geleitet, um den Schaltvorgang zu gewährleisten. Dieser Vorgang verursacht eine hohe Energieaufnahme. Für die Leseoperation wird gleicher- maßen ein beachtliches Zeitfenster benötigt, ebenfalls bedingt durch den Einfluss der Prozess- variation. Dem gegenüber stehen diverse Zuverlässigkeitsprobleme. Dazu gehören unter An- derem die Leseintereferenz und andere Degenerationspobleme, wie das des Time Dependent Di- electric Breakdowns (TDDB). Diese Zuverlässigkeitsprobleme sind wiederum auf die benötigten längeren Schaltzeiten zurückzuführen, welche in der Folge auch einen über längere Zeit an- liegenden Lese- bzw. Schreibstrom implizieren. Es ist daher notwendig, sowohl die Energie, als auch die Latenz zur Steigerung der Zuverlässigkeit zu reduzieren, um daraus einen potenziellen Kandidaten für ein on-Chip Speichersystem zu machen. In dieser Dissertation werden wir Entwurfsstrategien vorstellen, welche das Ziel verfolgen, die Herausforderungen des Cache-, Register- und Flip-Flop-Entwurfs anzugehen. Dies erre- ichen wir unter Zuhilfenahme eines Cross-Layer Ansatzes. Für Caches entwickelten wir ver- schiedene Ansätze auf Schaltkreisebene, welche sowohl auf der Speicherarchitekturebene, als auch auf der Systemebene in Bezug auf Energieaufnahme, Performanzsteigerung und Zuver- lässigkeitverbesserung evaluiert werden. Wir entwickeln eine Selbstabschalttechnik, sowohl für die Lese-, als auch die Schreiboperation von Caches. Diese ist in der Lage, den Abschluss der entsprechenden Operation dynamisch zu ermitteln. Nachdem der Abschluss erkannt wurde, wird die Lese- bzw. Schreiboperation sofort gestoppt, um Energie zu sparen. Zusätzlich limitiert die Selbstabschalttechnik die Dauer des Stromflusses durch die Speicherzelle, was wiederum das Auftreten von TDDB und Leseinterferenz bei Schreib- bzw. Leseoperationen re- duziert. Zur Verbesserung der Schreiblatenz heben wir den Schreibstrom an der Bitzelle an, um den magnetischen Schaltprozess zu beschleunigen. Um registerbankspezifische Anforderungen zu berücksichtigen, haben wir zusätzlich eine Multiport-Speicherarchitektur entworfen, welche eine einzigartige Eigenschaft der SOT-Zelle ausnutzt, um simultan Lese- und Schreiboperatio- nen auszuführen. Es ist daher möglich Lese/Schreib- Konfilkte auf Bitzellen-Ebene zu lösen, was sich wiederum in einer sehr viel einfacheren Multiport- Registerbankarchitektur nieder- schlägt. Zusätzlich zu den Speicheransätzen haben wir ebenfalls zwei Flip-Flop-Architekturen vorgestellt. Die erste ist eine nichtflüchtige non-Shadow Flip-Flop-Architektur, welche die Speicherzelle als aktive Komponente nutzt. Dies ermöglicht das sofortige An- und Ausschalten der Versorgungss- pannung und ist daher besonders gut für aggressives Powergating geeignet. Alles in Allem zeigt der vorgestellte Flip-Flop-Entwurf eine ähnliche Timing-Charakteristik wie die konventioneller CMOS Flip-Flops auf. Jedoch erlaubt er zur selben Zeit eine signifikante Reduktion der statis- chen Leistungsaufnahme im Vergleich zu nichtflüchtigen Shadow- Flip-Flops. Die zweite ist eine fehlertolerante Flip-Flop-Architektur, welche sich unanfällig gegenüber diversen Defekten und Fehlern verhält. Die Leistungsfähigkeit aller vorgestellten Techniken wird durch ausführliche Simulationen auf Schaltkreisebene verdeutlicht, welche weiter durch detaillierte Evaluationen auf Systemebene untermauert werden. Im Allgemeinen konnten wir verschiedene Techniken en- twickeln, die erhebliche Verbesserungen in Bezug auf Performanz, Energie und Zuverlässigkeit von spintronischen on-Chip Speichern, wie Caches, Register und Flip-Flops erreichen

Design and modelling of different SRAM's based on CNTFET 32nm technology

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn't require any refresh current. On the basis of acquired knowledge, we present different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.Comment: 15 Page