Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism

Processing, Structure, Properties, and Reliability of Metals for Microsystems

Research on the processing, structure, properties and reliability of metal films and metallic microdevice elements is reviewed. Recent research has demonstrated that inelastic deformation mechanisms of metallic films and microelements are a function of temperature, encapsulation, and dimension. Reduced dimension can lead to strengthening or softening, depending on the temperature and strain rate. These results will help in the analysis and prediction of the stress state of films and microelements as a function of their thermal history. Experimental characterization and modeling of stress evolution during film formation has also been undertaken. New microelectromechanical devices have been developed for in situ measurements of stress during processing, and experiments relating stress and structure evolution are underway for electrodeposition and reactive film formation as well as vapor deposition. Experiments relating current-induced stress evolution (electromigration) to the reliability of Cu based interconnects are also being carried out.Singapore-MIT Alliance (SMA

Influence of material quality and process-induced defects on semiconductor device performance and yield

An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations

An experimental investigation of thermally-induced deformation of 1 micron thick copper/tantalum/polymide high-density interconnect structures

A new technique to estimate the out-of-plane thermal expansion coefficient (CTE) of several 1 $\mu$m thick, spin-coated polyimides is introduced. Arrays of parallel copper and polyimide lines of various aspect ratios on Si substrate were imaged in air at room temperature and at 97\sp\circC using an atomic force microscope (AFM). The out-of-plane CTE of the polyimides was estimated by matching the experimental results with the predictions of finite element models with different out-of-plane parameters. For FPI-135 (6FCDA-TMOB) polyimide the out-of-plane CTE was found to be $\approx$260 ppm/\sp\circC, for FPI-136 (PMDA-6FDA-TFMOB) polyimide $\approx$120 ppm/\sp\circC. Polyimide lines with widths equal to or less than the film thickness of 1 $\mu$m showed less thermal expansion than wider lines. This was attributed to change of polyimide properties at the Cu/polyimide interface as a result of the reactive ion etching step of the structure manufacturing process. High density interconnect structures are subjected to 350\sp\circC during manufacturing. The mismatch between the Cu and the polyimide out-of-plane CTE leads to high shear stresses at the interfaces normal to the film plane during heating. The experimental observation of thermally induced deformation of Cu/Ta/polyimide line arrays as a result of RT-350\sp\circC-RT thermal cycle is discussed. In addition to classical high temperature deformation mechanisms (grain boundary sliding, grain elevation and Coble creep on the Cu surface), sliding at the Cu/Ta interface was observed using the AFM. It was found that the Cu/Ta interfacial sliding is a strong function of the Cu line width. 10 $\mu$m wide Cu lines were found to exhibit less Cu/Ta sliding compared to 1 $\mu$m wide Cu lines. This was attributed to ability of wide Cu lines relax the stresses using other mechanisms. A finite element model was constructed to analyze the Cu/Ta interfacial sliding

An experimental and finite element investigation of thermally induced inelastic deformation of single-level damascene copper high density interconnect structures

An atomic force microscope was used to investigate thermally induced deformation mechanisms in the areas of copper and polyimide vias in copper-polyimide interconnect structure, as a result of a thermal cycle to 350°C. The copper films exhibited evidence of copper grain boundary sliding, Coble creep, and voids formation. Cu-Ta interfacial sliding was observed in the Cu and polyimide via areas. The direction of the Cu-Ta sliding changes as the polyimide via size decreases. The polyimide experienced a residual deformation attributed to the Cu-Ta sliding and in-plane deformation of the copper vias. A finite element method was used to simulate the effect of Cu-Ta sliding on interfacial and liner plane stresses in Benzocyclobutane (BCB)-Cu and SiO2-Cu interconnect structures, heated to 400°C. A one rum thick element was used to produce a sliding effect at the Cu-Ta interface and at Cu grain boundary. The shear stresses in the SiO2-Cu system are completely relaxed by the Cu-Ta sliding. The Cu-Ta sliding increases the Ta liner plane stress in the BCB-Cu system to potentially damaging values, while the Ta stress in the SiO2-Cu system changes from tensile to compressive. Sliding at Cu grain boundary has a minor impact on Cu-Ta sliding and shear stress relaxation in the BCB-Cu system with large aspect ratio. A finite element technique was used to model the classical Nabarro-Herring creep in 1 mum square copper grain subjected to biaxial stresses of +/-10 MPa, at 800°C. A linear elastic mechanical analysis was carried out to simulate the mechanical loading and transient thermal analysis was utilized to simulate the diffusive vacancy flow process. The steady state flux components were used to predict the creep deformation of the grain and to estimate the creep strain rate at the boundaries. It was shown that the finite element procedure is capable of modeling the Nabarro-Herring creep, satisfactorily. The finite element result agrees with the analytical prediction within a factor of two

Nanomechanical characterization of BD (Low-K) thin films and Cu/BD multilayered stacks

Master'sMASTER OF ENGINEERIN

Low pressure chemical vapor deposition of copper films from CU(I)(HFAC)(TMVS)

Recently, copper has been found as a possible substitute for Al alloys because of its low resistivity (1.67 μΩ • cm) and potentially improved resistance to electromigration. Conventional physical vapor deposition (PVD) method do not provide the conformal deposition profile for the high density integrated circuit, therefore, chemical vapor deposition (CVD) has become the most promising method for the resulting conformal profile. In this work, a cold wall, single wafer, CVD tungsten reactor was used for the deposition of copper with Cu(I)(hfac)(tmvs). Film growth rates were between 100 to 800 A/min depending on processing conditions, and an Arrhenius type activation energy of 16.1 kcal/mole was obtained in the temperature region of 150-180 °C. No significant amount of contamination is detected in the copper films, and the resistivity of the films was routinely near 2.2 μΩ • cm when the film was 5000 A or more. The surface roughness of the films increased with increasing film thickness, and the crystal orientation was found as a function of growth rate. These obtained results demonstrated the feasibility of using Cu(I)(hfac)(tmvs) in the synthesis of high purity copper films using liquid injection by LPCVD

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Microbridge Formation for Low Resistance Interline Connection Using Pulsed Laser Techniques

MakeLink® technology has been applied in many semiconductor devices to achieve high performance. Sometimes one-type-link design doesn't make desirous links for all IC manufacturing processes. In this work, four new structures, called microbridge, were designed to form all types of link. Laser processing experiments were performed to verify the designs. The results show that two-lower-level-metal-line design has higher performance (low link resistance), higher productivity (broad energy window), and higher yield than the three-lower-level-metal-line design. Therefore, it can be considered as the optimal design from the processing point of view. Two-lower-level-metal-line with lateral gap structure provides better scalability and it can be used in next generation ICs. If high-speed is the primary concern, an advanced-lateral structure is best, corresponding to its much lower resistance. The reliability tests indicate that the median-times-to-failure of all test structures are greater than nine years in operating condition, presenting reasonable lifetimes for integrated circuits used in the market. A two-dimensional finite element plane models for microbridge formation is developed. Results are compared to the experiments with process windows to present their consistence. The model allowed for using different geometric parameters and metal-dielectric combinations optimizing the design. An optimal design diagram for the Al/SiO2 system is created to provide the designer with criteria to avoid the failure of structure. Trade-off requirements, such as process window and structure size, are also provided. Guidelines are obtained for the Cu/Low-K dielectric system