MARACAS: a real-time multicore VCPU scheduling framework

This paper describes a multicore scheduling and load-balancing framework called MARACAS, to address shared cache and memory bus contention. It builds upon prior work centered around the concept of virtual CPU (VCPU) scheduling. Threads are associated with VCPUs that have periodically replenished time budgets. VCPUs are guaranteed to receive their periodic budgets even if they are migrated between cores. A load balancing algorithm ensures VCPUs are mapped to cores to fairly distribute surplus CPU cycles, after ensuring VCPU timing guarantees. MARACAS uses surplus cycles to throttle the execution of threads running on specific cores when memory contention exceeds a certain threshold. This enables threads on other cores to make better progress without interference from co-runners. Our scheduling framework features a novel memory-aware scheduling approach that uses performance counters to derive an average memory request latency. We show that latency-based memory throttling is more effective than rate-based memory access control in reducing bus contention. MARACAS also supports cache-aware scheduling and migration using page recoloring to improve performance isolation amongst VCPUs. Experiments show how MARACAS reduces multicore resource contention, leading to improved task progress.http://www.cs.bu.edu/fac/richwest/papers/rtss_2016.pdfAccepted manuscrip

Positional Games

Positional games are a branch of combinatorics, researching a variety of two-player games, ranging from popular recreational games such as Tic-Tac-Toe and Hex, to purely abstract games played on graphs and hypergraphs. It is closely connected to many other combinatorial disciplines such as Ramsey theory, extremal graph and set theory, probabilistic combinatorics, and to computer science. We survey the basic notions of the field, its approaches and tools, as well as numerous recent advances, standing open problems and promising research directions.Comment: Submitted to Proceedings of the ICM 201

Asymptotically optimal parallel resource assignment with interference

Motivated by scheduling in multi-cell wireless networks and resource allocation in computer systems, we study a service facility with two types of users (or jobs) having heterogen

Vulnerable GPU Memory Management: Towards Recovering Raw Data from GPU

In this paper, we present that security threats coming with existing GPU memory management strategy are overlooked, which opens a back door for adversaries to freely break the memory isolation: they enable adversaries without any privilege in a computer to recover the raw memory data left by previous processes directly. More importantly, such attacks can work on not only normal multi-user operating systems, but also cloud computing platforms. To demonstrate the seriousness of such attacks, we recovered original data directly from GPU memory residues left by exited commodity applications, including Google Chrome, Adobe Reader, GIMP, Matlab. The results show that, because of the vulnerable memory management strategy, commodity applications in our experiments are all affected

Power series approximations for two-class generalized processor sharing systems

We develop power series approximations for a discrete-time queueing system with two parallel queues and one processor. If both queues are nonempty, a customer of queue 1 is served with probability beta, and a customer of queue 2 is served with probability 1-beta. If one of the queues is empty, a customer of the other queue is served with probability 1. We first describe the generating function U(z (1),z (2)) of the stationary queue lengths in terms of a functional equation, and show how to solve this using the theory of boundary value problems. Then, we propose to use the same functional equation to obtain a power series for U(z (1),z (2)) in beta. The first coefficient of this power series corresponds to the priority case beta=0, which allows for an explicit solution. All higher coefficients are expressed in terms of the priority case. Accurate approximations for the mean stationary queue lengths are obtained from combining truncated power series and Pad, approximation

A gang of thieves -- evolution of cooperative kleptoparasitism in the subfamily Argyrodinae (Araneae: Theridiidae)

This is the first comprehensive study of group-living behavior in kleptoparasitic Argyrodinae, and the first species level molecular phylogenetic analysis of the Argyrodinae (Araneae: Theridiidae). I included four research chapters in this dissertation. In Chapter 2, I showed the first empirical study of cooperative kleptoparasitism in Argyrodes miniaceus. The results showed that, at least at the level of foraging, group-living behavior has adaptive function of cooperation. Using a game theory model, the payoff of being cooperator in a group is greater than the payoff of being solitary. In Chapter 3, I concluded that kleptoparasites do not aggregate simply because the webs are large and can support multiple kleptoparasites. Social interactions among group members provide additional benefits that favor individuals remaining in groups. In Chapter 4, I concluded that group members could gain indirect benefit of fitness by cooperating with group members, who are potentially related individuals. This is because in group-living Argyrodes, group members are significantly more closely related than the individuals drawn randomly from the population in a small geographic scale. In Chapter 5, the phylogenetic analyses showed several independent origins of group-living behavior in different species groups. The evolutionary sequence of foraging strategies of Argyrodinae is from free-living to araneophagy, then to kleptoparasitism. The comparative analyses showed the specialization to large host is correlated with the evolution of group-living behavior. In addition, the processes of specialization thus becoming group-living may have caused diversification within species groups

Clustered Networks Protect Cooperation Against Catastrophic Collapse

Assuming a society of conditional cooperators (or moody conditional cooperators), this computational study proposes a new perspective on the structural advantage of social network clustering. Previous work focused on how clustered structure might encourage initial outbreaks of cooperation or defend against invasion by a few defectors. Instead, we explore the ability of a societal structure to retain cooperative norms in the face of widespread disturbances. Such disturbances may abstractly describe hardships like famine and economic recession, or the random spatial placement of a substantial numbers of pure defectors (or round-1 defectors) among a spatially-structured population of players in a laboratory game, etc. As links in tightly-clustered societies are reallocated to distant contacts, we observe that a society becomes increasingly susceptible to catastrophic cascades of defection: mutually-beneficial cooperative norms can be destroyed completely by modest shocks of defection. In contrast, networks with higher clustering coefficients can withstand larger shocks of defection before being forced to catastrophically-low levels of cooperation. We observe a remarkably-linear protective effect of clustering coefficient that becomes active above a critical level of clustering. Notably, both the critical level and the slope of this dependence is higher for decision-rule parameterizations that correspond to higher costs of cooperation. Our modeling framework provides a simple way to reinterpret the counter-intuitive and widely-cited human experiments of Suri and Watts (2011) while also affirming the classical intuition that network clustering and higher levels of cooperation should be positively associated

Fairness-aware scheduling on single-ISA heterogeneous multi-cores

Single-ISA heterogeneous multi-cores consisting of small (e.g., in-order) and big (e.g., out-of-order) cores dramatically improve energy- and power-efficiency by scheduling workloads on the most appropriate core type. A significant body of recent work has focused on improving system throughput through scheduling. However, none of the prior work has looked into fairness. Yet, guaranteeing that all threads make equal progress on heterogeneous multi-cores is of utmost importance for both multi-threaded and multi-program workloads to improve performance and quality-of-service. Furthermore, modern operating systems affinitize workloads to cores (pinned scheduling) which dramatically affects fairness on heterogeneous multi-cores. In this paper, we propose fairness-aware scheduling for single-ISA heterogeneous multi-cores, and explore two flavors for doing so. Equal-time scheduling runs each thread or workload on each core type for an equal fraction of the time, whereas equal-progress scheduling strives at getting equal amounts of work done on each core type. Our experimental results demonstrate an average 14% (and up to 25%) performance improvement over pinned scheduling through fairness-aware scheduling for homogeneous multi-threaded workloads; equal-progress scheduling improves performance by 32% on average for heterogeneous multi-threaded workloads. Further, we report dramatic improvements in fairness over prior scheduling proposals for multi-program workloads, while achieving system throughput comparable to throughput-optimized scheduling, and an average 21% improvement in throughput over pinned scheduling

VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs

ChipMulti-processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMPs. NOC must be carefully designed to provide low latencies and high throughput in the resource-constrained environment. To improve the network throughput, we propose the Very Long Packet Window (VLPW) architecture for the NOC router design that tries to close the throughput gap between state-of-the-art on-chip routers and the ideal interconnect fabric. To improve throughput, VLPW optimizes Switch Allocation (SA) efficiency. Existing SA normally applies Round-Robin scheduling to arbitrate among the packets targeting the same output port. However, this simple approach suffers from low arbitration efficiency and incurs low network throughput. Instead of relying solely on simple switch scheduling, the VLPW router design globally schedules all the input packets, resolves the output conflicts and achieves high throughput. With the VLPW architecture, we propose two scheduling schemes: Global Fairness and Global Diversity. Our simulation results show that the VLPW router achieves more than 20% throughput improvement without negative effects on zero-load latency